x86, mce: Cleanup symbols in intel thermal codes

[safe/jmp/linux-2.6] / arch / x86 / kernel / cpu / mcheck / p4.c

diff --git a/arch/x86/kernel/cpu/mcheck/p4.c b/arch/x86/kernel/cpu/mcheck/p4.c
index cb344ab..82cee10 100644 (file)
--- a/arch/x86/kernel/cpu/mcheck/p4.c
+++ b/arch/x86/kernel/cpu/mcheck/p4.c
@@ -51,7 +51,7 @@ static void intel_thermal_interrupt(struct pt_regs *regs)
        ack_APIC_irq();
 
        rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
-       therm_throt_process(msr_val & 0x1);
+       therm_throt_process(msr_val & THERM_STATUS_PROCHOT);
 }
 
 /* Thermal interrupt handler for this CPU setup: */
@@ -66,72 +66,11 @@ void smp_thermal_interrupt(struct pt_regs *regs)
        irq_exit();
 }
 
-/* P4/Xeon Thermal regulation detect and init: */
-static void intel_init_thermal(struct cpuinfo_x86 *c)
+void intel_set_thermal_handler(void)
 {
-       unsigned int cpu = smp_processor_id();
-       u32 l, h;
-
-       /* Thermal monitoring: */
-       if (!cpu_has(c, X86_FEATURE_ACPI))
-               return; /* -ENODEV */
-
-       /* Clock modulation: */
-       if (!cpu_has(c, X86_FEATURE_ACC))
-               return; /* -ENODEV */
-
-       /*
-        * First check if its enabled already, in which case there might
-        * be some SMM goo which handles it, so we can't even put a handler
-        * since it might be delivered via SMI already:
-        */
-       rdmsr(MSR_IA32_MISC_ENABLE, l, h);
-       h = apic_read(APIC_LVTTHMR);
-       if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
-               printk(KERN_DEBUG
-                      "CPU%d: Thermal monitoring handled by SMI\n", cpu);
-
-               return; /* -EBUSY */
-       }
-
-       /* Check whether a vector already exists, temporarily masked? */
-       if (h & APIC_VECTOR_MASK) {
-               printk(KERN_DEBUG
-                      "CPU%d: Thermal LVT vector (%#x) already installed\n",
-                      cpu, (h & APIC_VECTOR_MASK));
-
-               return; /* -EBUSY */
-       }
-
-       /*
-        * The temperature transition interrupt handler setup:
-        */
-
-       /* Our delivery vector: */
-       h = THERMAL_APIC_VECTOR;
-
-       /* We'll mask the thermal vector in the lapic till we're ready: */
-       h |= APIC_DM_FIXED | APIC_LVT_MASKED;
-       apic_write(APIC_LVTTHMR, h);
-
-       rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
-       wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03 , h);
-
-       /* Ok, we're good to go... */
        vendor_thermal_interrupt = intel_thermal_interrupt;
-
-       rdmsr(MSR_IA32_MISC_ENABLE, l, h);
-       wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
-
-       /* Unmask the thermal vector: */
-       l = apic_read(APIC_LVTTHMR);
-       apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
-
-       printk(KERN_INFO "CPU%d: Thermal monitoring enabled\n", cpu);
-
-       /* enable thermal throttle processing */
-       atomic_set(&therm_throt_en, 1);
 }
+
 #endif /* CONFIG_X86_MCE_P4THERMAL */
 
 /* P4/Xeon Extended MCE MSR retrieval, return 0 if unsupported */