Merge branch 'timers-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...

[safe/jmp/linux-2.6] / arch / x86 / kernel / cpu / intel.c

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 99468db..24ff26a 100644 (file)
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -11,7 +11,6 @@
 #include <asm/pgtable.h>
 #include <asm/msr.h>
 #include <asm/uaccess.h>
-#include <asm/ptrace.h>
 #include <asm/ds.h>
 #include <asm/bugs.h>
 
@@ -30,6 +29,19 @@
 
 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 {
+       /* Unmask CPUID levels if masked: */
+       if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
+               u64 misc_enable;
+
+               rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+
+               if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
+                       misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
+                       wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+                       c->cpuid_level = cpuid_eax(0);
+               }
+       }
+
        if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
                (c->x86 == 0x6 && c->x86_model >= 0x0e))
                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
@@ -41,6 +53,16 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
        if (c->x86 == 15 && c->x86_cache_alignment == 64)
                c->x86_cache_alignment = 128;
 #endif
+
+       /*
+        * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
+        * with P/T states and does not stop in deep C-states
+        */
+       if (c->x86_power & (1 << 8)) {
+               set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+               set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
+       }
+
 }
 
 #ifdef CONFIG_X86_32
@@ -174,7 +196,7 @@ static void __cpuinit srat_detect_node(void)
                node = first_node(node_online_map);
        numa_set_node(cpu, node);
 
-       printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
+       printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
 #endif
 }
 
@@ -242,6 +264,13 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 
        intel_workarounds(c);
 
+       /*
+        * Detect the extended topology information if available. This
+        * will reinitialise the initial_apicid which will be used
+        * in init_intel_cacheinfo()
+        */
+       detect_extended_topology(c);
+
        l2 = init_intel_cacheinfo(c);
        if (c->cpuid_level > 9) {
                unsigned eax = cpuid_eax(10);
@@ -262,6 +291,9 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
                ds_init_intel(c);
        }
 
+       if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
+               set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
+
 #ifdef CONFIG_X86_64
        if (c->x86 == 15)
                c->x86_cache_alignment = c->x86_clflush_size * 2;
@@ -307,13 +339,8 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
                set_cpu_cap(c, X86_FEATURE_P4);
        if (c->x86 == 6)
                set_cpu_cap(c, X86_FEATURE_P3);
-
-       if (cpu_has_bts)
-               ptrace_bts_init_intel(c);
-
 #endif
 
-       detect_extended_topology(c);
        if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
                /*
                 * let's use the legacy cpuid vector 0x1 and 0x4 for topology