[SPARC64]: Add dummy host controller to root of all PCI domains.

[safe/jmp/linux-2.6] / arch / sparc64 / kernel / pci_sabre.c

diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
index 64cdce8..a2f129d 100644 (file)
--- a/arch/sparc64/kernel/pci_sabre.c
+++ b/arch/sparc64/kernel/pci_sabre.c
@@ -319,6 +319,12 @@ static int __sabre_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 static int sabre_read_pci_cfg(struct pci_bus *bus, unsigned int devfn,
                              int where, int size, u32 *value)
 {
+       struct pci_pbm_info *pbm = bus->sysdata;
+
+       if (bus == pbm->pci_bus && devfn == 0x00)
+               return pci_host_bridge_read_pci_cfg(bus, devfn, where,
+                                                   size, value);
+
        if (!bus->number && sabre_out_of_range(devfn)) {
                switch (size) {
                case 1:
@@ -435,6 +441,12 @@ static int __sabre_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 static int sabre_write_pci_cfg(struct pci_bus *bus, unsigned int devfn,
                               int where, int size, u32 value)
 {
+       struct pci_pbm_info *pbm = bus->sysdata;
+
+       if (bus == pbm->pci_bus && devfn == 0x00)
+               return pci_host_bridge_write_pci_cfg(bus, devfn, where,
+                                                    size, value);
+
        if (bus->number)
                return __sabre_write_pci_cfg(bus, devfn, where, size, value);
 
@@ -862,51 +874,6 @@ static void sabre_register_error_handlers(struct pci_controller_info *p)
        sabre_write(base + SABRE_PCICTRL, tmp);
 }
 
-static void sabre_base_address_update(struct pci_dev *pdev, int resource)
-{
-       struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
-       struct resource *res;
-       unsigned long base;
-       u32 reg;
-       int where, size, is_64bit;
-
-       res = &pdev->resource[resource];
-       if (resource < 6) {
-               where = PCI_BASE_ADDRESS_0 + (resource * 4);
-       } else if (resource == PCI_ROM_RESOURCE) {
-               where = pdev->rom_base_reg;
-       } else {
-               /* Somebody might have asked allocation of a non-standard resource */
-               return;
-       }
-
-       is_64bit = 0;
-       if (res->flags & IORESOURCE_IO)
-               base = pbm->controller_regs + SABRE_IOSPACE;
-       else {
-               base = pbm->controller_regs + SABRE_MEMSPACE;
-               if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
-                   == PCI_BASE_ADDRESS_MEM_TYPE_64)
-                       is_64bit = 1;
-       }
-
-       size = res->end - res->start;
-       pci_read_config_dword(pdev, where, &reg);
-       reg = ((reg & size) |
-              (((u32)(res->start - base)) & ~size));
-       if (resource == PCI_ROM_RESOURCE) {
-               reg |= PCI_ROM_ADDRESS_ENABLE;
-               res->flags |= IORESOURCE_ROM_ENABLE;
-       }
-       pci_write_config_dword(pdev, where, reg);
-
-       /* This knows that the upper 32-bits of the address
-        * must be zero.  Our PCI common layer enforces this.
-        */
-       if (is_64bit)
-               pci_write_config_dword(pdev, where + 4, 0);
-}
-
 static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
 {
        struct pci_dev *pdev;
@@ -1040,7 +1007,6 @@ static void sabre_pbm_init(struct pci_controller_info *p, struct device_node *dp
        pbm->chip_type = PBM_CHIP_TYPE_SABRE;
        pbm->parent = p;
        pbm->prom_node = dp;
-       pbm->pci_first_slot = 1;
        pbm->pci_first_busno = p->pci_first_busno;
        pbm->pci_last_busno = p->pci_last_busno;
 
@@ -1097,9 +1063,7 @@ void sabre_init(struct device_node *dp, char *model_name)
 
        p->pbm_A.portid = upa_portid;
        p->index = pci_num_controllers++;
-       p->pbms_same_domain = 1;
        p->scan_bus = sabre_scan_bus;
-       p->base_address_update = sabre_base_address_update;
        p->pci_ops = &sabre_ops;
 
        /*