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Merge branch 'linus' into cont_syslog
[safe/jmp/linux-2.6] / arch / sh / kernel / cpu / sh4a / clock-sh7786.c
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index 57c13ba..597c9fb 100644 (file)
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -13,7 +13,6 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <linux/clk.h>
 #include <asm/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
@@ -23,8 +22,6 @@
  * from the platform code.
  */
 static struct clk extal_clk = {
-       .name           = "extal",
-       .id             = -1,
        .rate           = 33333333,
 };
 
@@ -46,8 +43,6 @@ static struct clk_ops pll_clk_ops = {
 };
 
 static struct clk pll_clk = {
-       .name           = "pll_clk",
-       .id             = -1,
        .ops            = &pll_clk_ops,
        .parent         = &extal_clk,
        .flags          = CLK_ENABLE_ON_INIT,
@@ -72,16 +67,16 @@ static struct clk_div4_table div4_table = {
 
 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
 
-#define DIV4(_str, _bit, _mask, _flags) \
-  SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
+#define DIV4(_bit, _mask, _flags) \
+  SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
 
 struct clk div4_clks[DIV4_NR] = {
-       [DIV4_P] = DIV4("peripheral_clk", 0, 0x0b40, 0),
-       [DIV4_DU] = DIV4("du_clk", 4, 0x0010, 0),
-       [DIV4_DDR] = DIV4("ddr_clk", 12, 0x0002, CLK_ENABLE_ON_INIT),
-       [DIV4_B] = DIV4("bus_clk", 16, 0x0360, CLK_ENABLE_ON_INIT),
-       [DIV4_SH] = DIV4("shyway_clk", 20, 0x0002, CLK_ENABLE_ON_INIT),
-       [DIV4_I] = DIV4("cpu_clk", 28, 0x0006, CLK_ENABLE_ON_INIT),
+       [DIV4_P] = DIV4(0, 0x0b40, 0),
+       [DIV4_DU] = DIV4(4, 0x0010, 0),
+       [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
+       [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
+       [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
+       [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
 };
 
 #define MSTPCR0                0xffc40030
@@ -97,40 +92,94 @@ enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
 
 static struct clk mstp_clks[MSTP_NR] = {
        /* MSTPCR0 */
-       [MSTP029] = SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
-       [MSTP028] = SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
-       [MSTP027] = SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
-       [MSTP026] = SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
-       [MSTP025] = SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
-       [MSTP024] = SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
-       [MSTP023] = SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0),
-       [MSTP022] = SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0),
-       [MSTP021] = SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
-       [MSTP020] = SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
-       [MSTP017] = SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
-       [MSTP016] = SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
-       [MSTP015] = SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0),
-       [MSTP014] = SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0),
-       [MSTP011] = SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0),
-       [MSTP010] = SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0),
-       [MSTP009] = SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
-       [MSTP008] = SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
-       [MSTP005] = SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
-       [MSTP004] = SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
-       [MSTP002] = SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
+       [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
+       [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
+       [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
+       [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
+       [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
+       [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
+       [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
+       [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
+       [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
+       [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
+       [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
+       [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
+       [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
+       [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
+       [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
+       [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
+       [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
+       [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
+       [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
+       [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
+       [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
 
        /* MSTPCR1 */
-       [MSTP112] = SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0),
-       [MSTP110] = SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0),
-       [MSTP109] = SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0),
-       [MSTP108] = SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0),
-       [MSTP105] = SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
-       [MSTP104] = SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
-       [MSTP103] = SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0),
-       [MSTP102] = SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0),
+       [MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
+       [MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
+       [MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
+       [MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
+       [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
+       [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
+       [MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
+       [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
 };
 
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+
 static struct clk_lookup lookups[] = {
+       /* main clocks */
+       CLKDEV_CON_ID("extal", &extal_clk),
+       CLKDEV_CON_ID("pll_clk", &pll_clk),
+
+       /* DIV4 clocks */
+       CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+       CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
+       CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
+       CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
+       CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
+       CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+
+       /* MSTP32 clocks */
+       {
+               /* SCIF5 */
+               .dev_id         = "sh-sci.5",
+               .con_id         = "sci_fck",
+               .clk            = &mstp_clks[MSTP029],
+       }, {
+               /* SCIF4 */
+               .dev_id         = "sh-sci.4",
+               .con_id         = "sci_fck",
+               .clk            = &mstp_clks[MSTP028],
+       }, {
+               /* SCIF3 */
+               .dev_id         = "sh-sci.3",
+               .con_id         = "sci_fck",
+               .clk            = &mstp_clks[MSTP027],
+       }, {
+               /* SCIF2 */
+               .dev_id         = "sh-sci.2",
+               .con_id         = "sci_fck",
+               .clk            = &mstp_clks[MSTP026],
+       }, {
+               /* SCIF1 */
+               .dev_id         = "sh-sci.1",
+               .con_id         = "sci_fck",
+               .clk            = &mstp_clks[MSTP025],
+       }, {
+               /* SCIF0 */
+               .dev_id         = "sh-sci.0",
+               .con_id         = "sci_fck",
+               .clk            = &mstp_clks[MSTP024],
+       },
+       CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
+       CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
+       CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
+       CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
+       CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
+       CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
+       CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
+       CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
        {
                /* TMU0 */
                .dev_id         = "sh_tmu.0",
@@ -191,7 +240,18 @@ static struct clk_lookup lookups[] = {
                .dev_id         = "sh_tmu.11",
                .con_id         = "tmu_fck",
                .clk            = &mstp_clks[MSTP011],
-       }
+       },
+       CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
+       CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
+       CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
+       CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
+       CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
+       CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
+       CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
+       CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
+       CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
+       CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
+       CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),
 };
 
 int __init arch_clk_init(void)
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