sh: convert initrd reservation to LMB.

[safe/jmp/linux-2.6] / arch / sh / Kconfig.cpu

diff --git a/arch/sh/Kconfig.cpu b/arch/sh/Kconfig.cpu
index d850184..ddf096c 100644 (file)
--- a/arch/sh/Kconfig.cpu
+++ b/arch/sh/Kconfig.cpu
@@ -12,6 +12,7 @@ config CPU_LITTLE_ENDIAN
 
 config CPU_BIG_ENDIAN
        bool "Big Endian"
+       depends on !CPU_SH5
 
 endchoice
 
@@ -67,7 +68,8 @@ config SH_STORE_QUEUES
 
 config SPECULATIVE_EXECUTION
        bool "Speculative subroutine return"
-       depends on CPU_SUBTYPE_SH7780 && EXPERIMENTAL
+       depends on EXPERIMENTAL
+       depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7786
        help
          This enables support for a speculative instruction fetch for
          subroutine return. There are various pitfalls associated with
@@ -75,11 +77,6 @@ config SPECULATIVE_EXECUTION
 
          If unsure, say N.
 
-config SH64_USER_MISALIGNED_FIXUP
-       def_bool y
-       prompt "Fixup misaligned loads/stores occurring in user mode"
-       depends on SUPERH64
-
 config SH64_ID2815_WORKAROUND
        bool "Include workaround for SH5-101 cut2 silicon defect ID2815"
        depends on CPU_SUBTYPE_SH5_101
@@ -87,9 +84,6 @@ config SH64_ID2815_WORKAROUND
 config CPU_HAS_INTEVT
        bool
 
-config CPU_HAS_MASKREG_IRQ
-       bool
-
 config CPU_HAS_IPR_IRQ
        bool
 
@@ -103,7 +97,7 @@ config CPU_HAS_SR_RB
          See <file:Documentation/sh/register-banks.txt> for further
          information on SR.RB and register banking in the kernel in general.
 
-config CPU_HAS_PTEA
+config CPU_HAS_PTEAEX
        bool
 
 config CPU_HAS_DSP