[POWERPC] Merge CPU features pertaining to icache coherency

[safe/jmp/linux-2.6] / arch / ppc / kernel / head_fsl_booke.S

diff --git a/arch/ppc/kernel/head_fsl_booke.S b/arch/ppc/kernel/head_fsl_booke.S
index eba5a5f..1f155d3 100644 (file)
--- a/arch/ppc/kernel/head_fsl_booke.S
+++ b/arch/ppc/kernel/head_fsl_booke.S
@@ -1,6 +1,4 @@
 /*
- * arch/ppc/kernel/head_fsl_booke.S
- *
  * Kernel execution entry point code.
  *
  *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
@@ -24,7 +22,7 @@
  *    Copyright 2002-2004 MontaVista Software, Inc.
  *      PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
  *    Copyright 2004 Freescale Semiconductor, Inc
- *      PowerPC e500 modifications, Kumar Gala <kumar.gala@freescale.com>
+ *      PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -32,7 +30,6 @@
  * option) any later version.
  */
 
-#include <linux/config.h>
 #include <linux/threads.h>
 #include <asm/processor.h>
 #include <asm/page.h>
@@ -209,7 +206,8 @@ skpinv:     addi    r6,r6,1                         /* Increment */
        rlwimi  r7,r3,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r3) */
        mtspr   SPRN_MAS0,r7
        tlbre
-       li      r6,0
+       mfspr   r6,SPRN_MAS1
+       rlwinm  r6,r6,0,2,0     /* clear IPROT */
        mtspr   SPRN_MAS1,r6
        tlbwe
        /* Invalidate TLB1 */
@@ -251,6 +249,8 @@ skpinv:     addi    r6,r6,1                         /* Increment */
        rlwimi  r7,r5,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r5) */
        mtspr   SPRN_MAS0,r7
        tlbre
+       mfspr   r8,SPRN_MAS1
+       rlwinm  r8,r8,0,2,0     /* clear IPROT */
        mtspr   SPRN_MAS1,r8
        tlbwe
        /* Invalidate TLB1 */
@@ -316,6 +316,7 @@ skpinv:     addi    r6,r6,1                         /* Increment */
         */
        lis     r2,DBCR0_IDM@h
        mtspr   SPRN_DBCR0,r2
+       isync
        /* clear any residual debug events */
        li      r2,-1
        mtspr   SPRN_DBSR,r2
@@ -426,14 +427,14 @@ skpinv:   addi    r6,r6,1                         /* Increment */
 
 interrupt_base:
        /* Critical Input Interrupt */
-       CRITICAL_EXCEPTION(0x0100, CriticalInput, UnknownException)
+       CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
 
        /* Machine Check Interrupt */
 #ifdef CONFIG_E200
        /* no RFMCI, MCSRRs on E200 */
-       CRITICAL_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
+       CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 #else
-       MCHECK_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
+       MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 #endif
 
        /* Data Storage Interrupt */
@@ -542,9 +543,9 @@ interrupt_base:
 #else
 #ifdef CONFIG_E200
        /* E200 treats 'normal' floating point instructions as FP Unavail exception */
-       EXCEPTION(0x0800, FloatingPointUnavailable, ProgramCheckException, EXC_XFER_EE)
+       EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
 #else
-       EXCEPTION(0x0800, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
+       EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
 #endif
 #endif
 
@@ -554,20 +555,20 @@ interrupt_base:
        EXC_XFER_EE_LITE(0x0c00, DoSyscall)
 
        /* Auxillary Processor Unavailable Interrupt */
-       EXCEPTION(0x2900, AuxillaryProcessorUnavailable, UnknownException, EXC_XFER_EE)
+       EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
 
        /* Decrementer Interrupt */
        DECREMENTER_EXCEPTION
 
        /* Fixed Internal Timer Interrupt */
        /* TODO: Add FIT support */
-       EXCEPTION(0x3100, FixedIntervalTimer, UnknownException, EXC_XFER_EE)
+       EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
 
        /* Watchdog Timer Interrupt */
 #ifdef CONFIG_BOOKE_WDT
        CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
 #else
-       CRITICAL_EXCEPTION(0x3200, WatchdogTimer, UnknownException)
+       CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
 #endif
 
        /* Data TLB Error Interrupt */
@@ -696,21 +697,21 @@ interrupt_base:
        addi    r3,r1,STACK_FRAME_OVERHEAD
        EXC_XFER_EE_LITE(0x2010, KernelSPE)
 #else
-       EXCEPTION(0x2020, SPEUnavailable, UnknownException, EXC_XFER_EE)
+       EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
 #endif /* CONFIG_SPE */
 
        /* SPE Floating Point Data */
 #ifdef CONFIG_SPE
        EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
 #else
-       EXCEPTION(0x2040, SPEFloatingPointData, UnknownException, EXC_XFER_EE)
+       EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
 #endif /* CONFIG_SPE */
 
        /* SPE Floating Point Round */
-       EXCEPTION(0x2050, SPEFloatingPointRound, UnknownException, EXC_XFER_EE)
+       EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
 
        /* Performance Monitor */
-       EXCEPTION(0x2060, PerformanceMonitor, PerformanceMonitorException, EXC_XFER_STD)
+       EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
 
 
        /* Debug Interrupt */
@@ -891,7 +892,6 @@ load_up_spe:
        REST_GPR(9, r11)
        REST_GPR(12, r11)
        lwz     r11,GPR11(r11)
-       SYNC
        rfi
 
 /*
@@ -955,7 +955,6 @@ _GLOBAL(giveup_altivec)
 _GLOBAL(giveup_spe)
        mfmsr   r5
        oris    r5,r5,MSR_SPE@h
-       SYNC
        mtmsr   r5                      /* enable use of SPE now */
        isync
        cmpi    0,r3,0
@@ -1002,12 +1001,15 @@ _GLOBAL(giveup_fpu)
 _GLOBAL(abort)
        li      r13,0
         mtspr   SPRN_DBCR0,r13         /* disable all debug events */
+       isync
        mfmsr   r13
        ori     r13,r13,MSR_DE@l        /* Enable Debug Events */
        mtmsr   r13
+       isync
         mfspr   r13,SPRN_DBCR0
         lis    r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
         mtspr   SPRN_DBCR0,r13
+       isync
 
 _GLOBAL(set_context)
 
@@ -1028,10 +1030,14 @@ _GLOBAL(set_context)
  * goes at the beginning of the data segment, which is page-aligned.
  */
        .data
-_GLOBAL(sdata)
-_GLOBAL(empty_zero_page)
+       .align  12
+       .globl  sdata
+sdata:
+       .globl  empty_zero_page
+empty_zero_page:
        .space  4096
-_GLOBAL(swapper_pg_dir)
+       .globl  swapper_pg_dir
+swapper_pg_dir:
        .space  4096
 
 /* Reserved 4k for the critical exception stack & 4k for the machine
@@ -1040,13 +1046,15 @@ _GLOBAL(swapper_pg_dir)
         .align 12
 exception_stack_bottom:
        .space  BOOKE_EXCEPTION_STACK_SIZE * NR_CPUS
-_GLOBAL(exception_stack_top)
+       .globl  exception_stack_top
+exception_stack_top:
 
 /*
  * This space gets a copy of optional info passed to us by the bootstrap
  * which is used to pass parameters into the kernel like root=/dev/sda1, etc.
  */
-_GLOBAL(cmd_line)
+       .globl  cmd_line
+cmd_line:
        .space  512
 
 /*
@@ -1055,4 +1063,3 @@ _GLOBAL(cmd_line)
  */
 abatron_pteptrs:
        .space  8
-