* option) any later version.
*/
-#include <linux/config.h>
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
-#include <linux/root_dev.h>
+#include <linux/of_platform.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
-#include <asm/mpc85xx.h>
-#include <asm/prom.h>
#include <asm/mpic.h>
#include <mm/mmu_decl.h>
#include <asm/udbg.h>
#include <sysdev/fsl_soc.h>
-#include "mpc85xx.h"
+#include <sysdev/fsl_pci.h>
-#ifndef CONFIG_PCI
-unsigned long isa_io_base = 0;
-unsigned long isa_mem_base = 0;
+#ifdef CONFIG_CPM2
+#include <asm/cpm2.h>
+#include <sysdev/cpm2_pic.h>
#endif
-/*
- * Internal interrupts are all Level Sensitive, and Positive Polarity
- *
- * Note: Likely, this table and the following function should be
- * obtained and derived from the OF Device Tree.
- */
-static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
- MPC85XX_INTERNAL_IRQ_SENSES,
- 0x0, /* External 0: */
-#if defined(CONFIG_PCI)
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 1: PCI slot 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 2: PCI slot 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 3: PCI slot 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 4: PCI slot 3 */
-#else
- 0x0, /* External 1: */
- 0x0, /* External 2: */
- 0x0, /* External 3: */
- 0x0, /* External 4: */
-#endif
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
- 0x0, /* External 6: */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 7: PHY */
- 0x0, /* External 8: */
- 0x0, /* External 9: */
- 0x0, /* External 10: */
- 0x0, /* External 11: */
-};
-
#ifdef CONFIG_PCI
-/*
- * interrupt routing
- */
-
-int
-mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
- static char pci_irq_table[][4] =
- /*
- * This is little evil, but works around the fact
- * that revA boards have IDSEL starting at 18
- * and others boards (older) start at 12
- *
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {
- {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 2 */
- {PIRQD, PIRQA, PIRQB, PIRQC},
- {PIRQC, PIRQD, PIRQA, PIRQB},
- {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 5 */
- {0, 0, 0, 0}, /* -- */
- {0, 0, 0, 0}, /* -- */
- {0, 0, 0, 0}, /* -- */
- {0, 0, 0, 0}, /* -- */
- {0, 0, 0, 0}, /* -- */
- {0, 0, 0, 0}, /* -- */
- {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 12 */
- {PIRQD, PIRQA, PIRQB, PIRQC},
- {PIRQC, PIRQD, PIRQA, PIRQB},
- {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 15 */
- {0, 0, 0, 0}, /* -- */
- {0, 0, 0, 0}, /* -- */
- {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 18 */
- {PIRQD, PIRQA, PIRQB, PIRQC},
- {PIRQC, PIRQD, PIRQA, PIRQB},
- {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 21 */
- };
-
- const long min_idsel = 2, max_idsel = 21, irqs_per_slot = 4;
- return PCI_IRQ_TABLE_LOOKUP;
-}
-
-int
-mpc85xx_exclude_device(u_char bus, u_char devfn)
+static int mpc85xx_exclude_device(struct pci_controller *hose,
+ u_char bus, u_char devfn)
{
if (bus == 0 && PCI_SLOT(devfn) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;
else
return PCIBIOS_SUCCESSFUL;
}
-
#endif /* CONFIG_PCI */
+#ifdef CONFIG_CPM2
-void __init mpc85xx_ads_pic_init(void)
+static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
{
- struct mpic *mpic1;
- phys_addr_t OpenPIC_PAddr;
-
- /* Determine the Physical Address of the OpenPIC regs */
- OpenPIC_PAddr = get_immrbase() + MPC85xx_OPENPIC_OFFSET;
-
- mpic1 = mpic_alloc(OpenPIC_PAddr,
- MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
- 4, MPC85xx_OPENPIC_IRQ_OFFSET, 0, 250,
- mpc85xx_ads_openpic_initsenses,
- sizeof(mpc85xx_ads_openpic_initsenses),
- " OpenPIC ");
- BUG_ON(mpic1 == NULL);
- mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200);
- mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10280);
- mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10300);
- mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10380);
- mpic_assign_isu(mpic1, 4, OpenPIC_PAddr + 0x10400);
- mpic_assign_isu(mpic1, 5, OpenPIC_PAddr + 0x10480);
- mpic_assign_isu(mpic1, 6, OpenPIC_PAddr + 0x10500);
- mpic_assign_isu(mpic1, 7, OpenPIC_PAddr + 0x10580);
-
- /* dummy mappings to get to 48 */
- mpic_assign_isu(mpic1, 8, OpenPIC_PAddr + 0x10600);
- mpic_assign_isu(mpic1, 9, OpenPIC_PAddr + 0x10680);
- mpic_assign_isu(mpic1, 10, OpenPIC_PAddr + 0x10700);
- mpic_assign_isu(mpic1, 11, OpenPIC_PAddr + 0x10780);
-
- /* External ints */
- mpic_assign_isu(mpic1, 12, OpenPIC_PAddr + 0x10000);
- mpic_assign_isu(mpic1, 13, OpenPIC_PAddr + 0x10080);
- mpic_assign_isu(mpic1, 14, OpenPIC_PAddr + 0x10100);
- mpic_init(mpic1);
+ int cascade_irq;
+
+ while ((cascade_irq = cpm2_get_irq()) >= 0)
+ generic_handle_irq(cascade_irq);
+
+ desc->chip->eoi(irq);
+}
+
+#endif /* CONFIG_CPM2 */
+
+static void __init mpc85xx_ads_pic_init(void)
+{
+ struct mpic *mpic;
+ struct resource r;
+ struct device_node *np = NULL;
+#ifdef CONFIG_CPM2
+ int irq;
+#endif
+
+ np = of_find_node_by_type(np, "open-pic");
+ if (!np) {
+ printk(KERN_ERR "Could not find open-pic node\n");
+ return;
+ }
+
+ if (of_address_to_resource(np, 0, &r)) {
+ printk(KERN_ERR "Could not map mpic register space\n");
+ of_node_put(np);
+ return;
+ }
+
+ mpic = mpic_alloc(np, r.start,
+ MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+ 0, 256, " OpenPIC ");
+ BUG_ON(mpic == NULL);
+ of_node_put(np);
+
+ mpic_init(mpic);
+
+#ifdef CONFIG_CPM2
+ /* Setup CPM2 PIC */
+ np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
+ if (np == NULL) {
+ printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
+ return;
+ }
+ irq = irq_of_parse_and_map(np, 0);
+
+ cpm2_pic_init(np);
+ of_node_put(np);
+ set_irq_chained_handler(irq, cpm2_cascade);
+#endif
}
/*
* Setup the architecture
*/
+#ifdef CONFIG_CPM2
+struct cpm_pin {
+ int port, pin, flags;
+};
+
+static const struct cpm_pin mpc8560_ads_pins[] = {
+ /* SCC1 */
+ {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+ /* SCC2 */
+ {3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+ /* FCC2 */
+ {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+ {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK14 */
+ {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK13 */
+
+ /* FCC3 */
+ {1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 7, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+ {1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+ {2, 16, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* CLK16 */
+ {2, 17, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* CLK15 */
+};
+
+static void __init init_ioports(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(mpc8560_ads_pins); i++) {
+ const struct cpm_pin *pin = &mpc8560_ads_pins[i];
+ cpm2_set_pin(pin->port, pin->pin, pin->flags);
+ }
+
+ cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
+ cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
+ cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
+ cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
+ cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
+}
+#endif
+
static void __init mpc85xx_ads_setup_arch(void)
{
- struct device_node *cpu;
+#ifdef CONFIG_PCI
struct device_node *np;
+#endif
if (ppc_md.progress)
ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
- cpu = of_find_node_by_type(NULL, "cpu");
- if (cpu != 0) {
- unsigned int *fp;
-
- fp = (int *)get_property(cpu, "clock-frequency", NULL);
- if (fp != 0)
- loops_per_jiffy = *fp / HZ;
- else
- loops_per_jiffy = 50000000 / HZ;
- of_node_put(cpu);
- }
+#ifdef CONFIG_CPM2
+ cpm2_reset();
+ init_ioports();
+#endif
#ifdef CONFIG_PCI
- for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
- add_bridge(np);
+ for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
+ fsl_add_bridge(np, 1);
- ppc_md.pci_swizzle = common_swizzle;
- ppc_md.pci_map_irq = mpc85xx_map_irq;
ppc_md.pci_exclude_device = mpc85xx_exclude_device;
#endif
-
-#ifdef CONFIG_ROOT_NFS
- ROOT_DEV = Root_NFS;
-#else
- ROOT_DEV = Root_HDA1;
-#endif
}
-void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
+static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
{
uint pvid, svid, phid1;
uint memsize = total_memory;
seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
}
+static struct of_device_id __initdata of_bus_ids[] = {
+ { .name = "soc", },
+ { .type = "soc", },
+ { .name = "cpm", },
+ { .name = "localbus", },
+ {},
+};
+
+static int __init declare_of_platform_devices(void)
+{
+ of_platform_bus_probe(NULL, of_bus_ids, NULL);
+
+ return 0;
+}
+machine_device_initcall(mpc85xx_ads, declare_of_platform_devices);
+
/*
* Called very early, device-tree isn't unflattened
*/
static int __init mpc85xx_ads_probe(void)
{
- /* We always match for now, eventually we should look at the flat
- dev tree to ensure this is the board we are suppose to run on
- */
- return 1;
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "MPC85xxADS");
}
define_machine(mpc85xx_ads) {
.init_IRQ = mpc85xx_ads_pic_init,
.show_cpuinfo = mpc85xx_ads_show_cpuinfo,
.get_irq = mpic_get_irq,
- .restart = mpc85xx_restart,
+ .restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff