Staging: cxt1e1: fix cxt1e1 module names

[safe/jmp/linux-2.6] / arch / powerpc / mm / tlb_nohash_low.S

diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index 3037911..bbdc5b5 100644 (file)
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -39,7 +39,7 @@
 /*
  * 40x implementation needs only tlbil_va
  */
-_GLOBAL(_tlbil_va)
+_GLOBAL(__tlbil_va)
        /* We run the search with interrupts disabled because we have to change
         * the PID and I don't want to preempt when that happens.
         */
@@ -71,7 +71,7 @@ _GLOBAL(_tlbil_va)
  * 440 implementation uses tlbsx/we for tlbil_va and a full sweep
  * of the TLB for everything else.
  */
-_GLOBAL(_tlbil_va)
+_GLOBAL(__tlbil_va)
        mfspr   r5,SPRN_MMUCR
        rlwimi  r5,r4,0,24,31                   /* Set TID */
 
@@ -124,8 +124,6 @@ _GLOBAL(_tlbil_pid)
  * to have the larger code path before the _SECTION_ELSE
  */
 
-#define MMUCSR0_TLBFI  (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
-                        MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
 /*
  * Flush MMU TLB on the local processor
  */
@@ -170,7 +168,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBILX)
  * Flush MMU TLB for a particular address, but only on the local processor
  * (no broadcast)
  */
-_GLOBAL(_tlbil_va)
+_GLOBAL(__tlbil_va)
        mfmsr   r10
        wrteei  0
        slwi    r4,r4,16
@@ -191,6 +189,85 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
        isync
 1:     wrtee   r10
        blr
+#elif defined(CONFIG_PPC_BOOK3E)
+/*
+ * New Book3E (>= 2.06) implementation
+ *
+ * Note: We may be able to get away without the interrupt masking stuff
+ * if we save/restore MAS6 on exceptions that might modify it
+ */
+_GLOBAL(_tlbil_pid)
+       slwi    r4,r3,MAS6_SPID_SHIFT
+       mfmsr   r10
+       wrteei  0
+       mtspr   SPRN_MAS6,r4
+       PPC_TLBILX_PID(0,0)
+       wrtee   r10
+       msync
+       isync
+       blr
+
+_GLOBAL(_tlbil_pid_noind)
+       slwi    r4,r3,MAS6_SPID_SHIFT
+       mfmsr   r10
+       ori     r4,r4,MAS6_SIND
+       wrteei  0
+       mtspr   SPRN_MAS6,r4
+       PPC_TLBILX_PID(0,0)
+       wrtee   r10
+       msync
+       isync
+       blr
+
+_GLOBAL(_tlbil_all)
+       PPC_TLBILX_ALL(0,0)
+       msync
+       isync
+       blr
+
+_GLOBAL(_tlbil_va)
+       mfmsr   r10
+       wrteei  0
+       cmpwi   cr0,r6,0
+       slwi    r4,r4,MAS6_SPID_SHIFT
+       rlwimi  r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
+       beq     1f
+       rlwimi  r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
+1:     mtspr   SPRN_MAS6,r4            /* assume AS=0 for now */
+       PPC_TLBILX_VA(0,r3)
+       msync
+       isync
+       wrtee   r10
+       blr
+
+_GLOBAL(_tlbivax_bcast)
+       mfmsr   r10
+       wrteei  0
+       cmpwi   cr0,r6,0
+       slwi    r4,r4,MAS6_SPID_SHIFT
+       rlwimi  r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
+       beq     1f
+       rlwimi  r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
+1:     mtspr   SPRN_MAS6,r4            /* assume AS=0 for now */
+       PPC_TLBIVAX(0,r3)
+       eieio
+       tlbsync
+       sync
+       wrtee   r10
+       blr
+
+_GLOBAL(set_context)
+#ifdef CONFIG_BDI_SWITCH
+       /* Context switch the PTE pointer for the Abatron BDI2000.
+        * The PGDIR is the second parameter.
+        */
+       lis     r5, abatron_pteptrs@h
+       ori     r5, r5, abatron_pteptrs@l
+       stw     r4, 0x4(r5)
+#endif
+       mtspr   SPRN_PID,r3
+       isync                   /* Force context change */
+       blr
 #else
 #error Unsupported processor type !
 #endif