Merge branch 'linux-2.6'

[safe/jmp/linux-2.6] / arch / powerpc / kernel / head_32.S

diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index fdd34db..c897203 100644 (file)
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -22,7 +22,6 @@
  *
  */
 
-#include <linux/config.h>
 #include <asm/reg.h>
 #include <asm/page.h>
 #include <asm/mmu.h>
@@ -120,10 +119,25 @@ __start:
  * because OF may have I/O devices mapped into that area
  * (particularly on CHRP).
  */
+#ifdef CONFIG_PPC_MULTIPLATFORM
        cmpwi   0,r5,0
        beq     1f
        bl      prom_init
        trap
+#endif
+
+/*
+ * Check for BootX signature when supporting PowerMac and branch to
+ * appropriate trampoline if it's present
+ */
+#ifdef CONFIG_PPC_PMAC
+1:     lis     r31,0x426f
+       ori     r31,r31,0x6f58
+       cmpw    0,r3,r31
+       bne     1f
+       bl      bootx_init
+       trap
+#endif /* CONFIG_PPC_PMAC */
 
 1:     mr      r31,r3                  /* save parameters */
        mr      r30,r4
@@ -330,12 +344,7 @@ i##n:                                                              \
 /* System reset */
 /* core99 pmac starts the seconary here by changing the vector, and
    putting it back to what it was (unknown_exception) when done.  */
-#if defined(CONFIG_GEMINI) && defined(CONFIG_SMP)
-       . = 0x100
-       b       __secondary_start_gemini
-#else
        EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
-#endif
 
 /* Machine check */
 /*
@@ -423,6 +432,13 @@ Alignment:
 /* Floating-point unavailable */
        . = 0x800
 FPUnavailable:
+BEGIN_FTR_SECTION
+/*
+ * Certain Freescale cores don't have a FPU and treat fp instructions
+ * as a FP Unavailable exception.  Redirect to illegal/emulation handling.
+ */
+       b       ProgramCheck
+END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
        EXCEPTION_PROLOG
        bne     load_up_fpu             /* if from user, just load it up */
        addi    r3,r1,STACK_FRAME_OVERHEAD
@@ -453,16 +469,11 @@ SystemCall:
  * by executing an altivec instruction.
  */
        . = 0xf00
-       b       Trap_0f
+       b       PerformanceMonitor
 
        . = 0xf20
        b       AltiVecUnavailable
 
-Trap_0f:
-       EXCEPTION_PROLOG
-       addi    r3,r1,STACK_FRAME_OVERHEAD
-       EXC_XFER_EE(0xf00, unknown_exception)
-
 /*
  * Handle TLB miss for instruction on 603/603e.
  * Note: we get an alternate set of r0 - r3 to use automatically.
@@ -704,8 +715,14 @@ AltiVecUnavailable:
 #ifdef CONFIG_ALTIVEC
        bne     load_up_altivec         /* if from user, just load it up */
 #endif /* CONFIG_ALTIVEC */
+       addi    r3,r1,STACK_FRAME_OVERHEAD
        EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
 
+PerformanceMonitor:
+       EXCEPTION_PROLOG
+       addi    r3,r1,STACK_FRAME_OVERHEAD
+       EXC_XFER_STD(0xf00, performance_monitor_exception)
+
 #ifdef CONFIG_ALTIVEC
 /* Note that the AltiVec support is closely modeled after the FP
  * support.  Changes to one are likely to be applicable to the
@@ -957,6 +974,13 @@ __secondary_start_gemini:
         b       __secondary_start
 #endif /* CONFIG_GEMINI */
 
+       .globl __secondary_start_mpc86xx
+__secondary_start_mpc86xx:
+       mfspr   r3, SPRN_PIR
+       stw     r3, __secondary_hold_acknowledge@l(0)
+       mr      r24, r3                 /* cpu # */
+       b       __secondary_start
+
        .globl  __secondary_start_pmac_0
 __secondary_start_pmac_0:
        /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
@@ -1072,7 +1096,12 @@ load_up_mmu:
        LOAD_BAT(1,r3,r4,r5)
        LOAD_BAT(2,r3,r4,r5)
        LOAD_BAT(3,r3,r4,r5)
-
+BEGIN_FTR_SECTION
+       LOAD_BAT(4,r3,r4,r5)
+       LOAD_BAT(5,r3,r4,r5)
+       LOAD_BAT(6,r3,r4,r5)
+       LOAD_BAT(7,r3,r4,r5)
+END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
        blr
 
 /*