powerpc/fsl-booke: Enable L1 cache on e500v1/e500v2/e500mc CPUs

[safe/jmp/linux-2.6] / arch / powerpc / include / asm / dcr-regs.h

diff --git a/arch/powerpc/include/asm/dcr-regs.h b/arch/powerpc/include/asm/dcr-regs.h
index f15296c..828e3aa 100644 (file)
--- a/arch/powerpc/include/asm/dcr-regs.h
+++ b/arch/powerpc/include/asm/dcr-regs.h
@@ -68,6 +68,13 @@
 #define SDR0_UART3             0x0123
 #define SDR0_CUST0             0x4000
 
+/* SDR for 405EZ */
+#define DCRN_SDR_ICINTSTAT     0x4510
+#define ICINTSTAT_ICRX 0x80000000
+#define ICINTSTAT_ICTX0        0x40000000
+#define ICINTSTAT_ICTX1 0x20000000
+#define ICINTSTAT_ICTX 0x60000000
+
 /* SDRs (460EX/460GT) */
 #define SDR0_ETH_CFG           0x4103
 #define SDR0_ETH_CFG_ECS       0x00000100      /* EMAC int clk source */