MIPS: TXx9: Add SRAMC support

[safe/jmp/linux-2.6] / arch / mips / txx9 / generic / setup_tx4938.c

diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
index 25819ff..eb20801 100644 (file)
--- a/arch/mips/txx9/generic/setup_tx4938.c
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -23,6 +23,8 @@
 #include <asm/txx9tmr.h>
 #include <asm/txx9pio.h>
 #include <asm/txx9/generic.h>
+#include <asm/txx9/ndfmc.h>
+#include <asm/txx9/dmac.h>
 #include <asm/txx9/tx4938.h>
 
 static void __init tx4938_wdr_init(void)
@@ -92,7 +94,7 @@ void __init tx4938_setup(void)
 {
        int i;
        __u32 divmode;
-       int cpuclk = 0;
+       unsigned int cpuclk = 0;
        u64 ccfg;
 
        txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE,
@@ -238,11 +240,6 @@ void __init tx4938_setup(void)
        for (i = 0; i < TX4938_NR_TMR; i++)
                txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
 
-       /* DMA */
-       for (i = 0; i < 2; i++)
-               ____raw_writeq(TX4938_DMA_MCR_MSTEN,
-                              (void __iomem *)(TX4938_DMA_REG(i) + 0x50));
-
        /* PIO */
        txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
        __raw_writel(0, &tx4938_pioptr->maskcpu);
@@ -382,6 +379,58 @@ void __init tx4938_ata_init(unsigned int irq, unsigned int shift, int tune)
                platform_device_put(pdev);
 }
 
+void __init tx4938_ndfmc_init(unsigned int hold, unsigned int spw)
+{
+       struct txx9ndfmc_platform_data plat_data = {
+               .shift = 1,
+               .gbus_clock = txx9_gbus_clock,
+               .hold = hold,
+               .spw = spw,
+               .ch_mask = 1,
+       };
+       unsigned long baseaddr = TX4938_NDFMC_REG & 0xfffffffffULL;
+
+#ifdef __BIG_ENDIAN
+       baseaddr += 4;
+#endif
+       if ((__raw_readq(&tx4938_ccfgptr->pcfg) &
+            (TX4938_PCFG_ATA_SEL|TX4938_PCFG_ISA_SEL|TX4938_PCFG_NDF_SEL)) ==
+           TX4938_PCFG_NDF_SEL)
+               txx9_ndfmc_init(baseaddr, &plat_data);
+}
+
+void __init tx4938_dmac_init(int memcpy_chan0, int memcpy_chan1)
+{
+       struct txx9dmac_platform_data plat_data = {
+               .have_64bit_regs = true,
+       };
+       int i;
+
+       for (i = 0; i < 2; i++) {
+               plat_data.memcpy_chan = i ? memcpy_chan1 : memcpy_chan0;
+               txx9_dmac_init(i, TX4938_DMA_REG(i) & 0xfffffffffULL,
+                              TXX9_IRQ_BASE + TX4938_IR_DMA(i, 0),
+                              &plat_data);
+       }
+}
+
+void __init tx4938_aclc_init(void)
+{
+       u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg);
+
+       if ((pcfg & TX4938_PCFG_SEL2) &&
+           !(pcfg & TX4938_PCFG_ETH0_SEL))
+               txx9_aclc_init(TX4938_ACLC_REG & 0xfffffffffULL,
+                              TXX9_IRQ_BASE + TX4938_IR_ACLC,
+                              1, 0, 1);
+}
+
+void __init tx4938_sramc_init(void)
+{
+       if (tx4938_sram_resource.start)
+               txx9_sramc_init(&tx4938_sram_resource);
+}
+
 static void __init tx4938_stop_unused_modules(void)
 {
        __u64 pcfg, rst = 0, ckd = 0;