[MIPS] Declare some pci variables in header file

[safe/jmp/linux-2.6] / arch / mips / pci / pci-sb1250.c

diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index 7cca3bd..bf63959 100644 (file)
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -30,7 +30,6 @@
  * kernel mapped memory.  Hopefully neither of these should be a huge
  * problem.
  */
-#include <linux/config.h>
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/kernel.h>
@@ -50,8 +49,8 @@
  * Macros for calculating offsets into config space given a device
  * structure or dev/fun/reg
  */
-#define CFGOFFSET(bus,devfn,where) (((bus)<<16) + ((devfn)<<8) + (where))
-#define CFGADDR(bus,devfn,where)   CFGOFFSET((bus)->number,(devfn),where)
+#define CFGOFFSET(bus, devfn, where) (((bus)<<16) + ((devfn)<<8) + (where))
+#define CFGADDR(bus, devfn, where)   CFGOFFSET((bus)->number, (devfn), where)
 
 static void *cfg_space;
 
@@ -85,7 +84,7 @@ static inline void WRITECFG32(u32 addr, u32 data)
        *(u32 *) (cfg_space + (addr & ~3)) = data;
 }
 
-int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
        return dev->irq;
 }
@@ -208,9 +207,9 @@ struct pci_controller sb1250_controller = {
 
 static int __init sb1250_pcibios_init(void)
 {
+       void __iomem *io_map_base;
        uint32_t cmdreg;
        uint64_t reg;
-       extern int pci_probe_only;
 
        /* CFE will assign PCI resources */
        pci_probe_only = 1;
@@ -229,7 +228,7 @@ static int __init sb1250_pcibios_init(void)
        /*
         * See if the PCI bus has been configured by the firmware.
         */
-       reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG));
+       reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
        if (!(reg & M_SYS_PCI_HOST)) {
                sb1250_bus_status |= PCI_DEVICE_MODE;
        } else {
@@ -254,11 +253,9 @@ static int __init sb1250_pcibios_init(void)
         * works correctly with most of Linux's drivers.
         * XXX ehs: Should this happen in PCI Device mode?
         */
-
-       set_io_port_base((unsigned long)
-                        ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 65536));
-       isa_slot_offset = (unsigned long)
-           ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024 * 1024);
+       io_map_base = ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 1024 * 1024);
+       sb1250_controller.io_map_base = io_map_base;
+       set_io_port_base((unsigned long)io_map_base);
 
 #ifdef CONFIG_SIBYTE_HAS_LDT
        /*