#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
-#include <asm/ptrace.h>
#include <asm/hardirq.h>
+#include <asm/i8253.h>
#include <asm/irq.h>
#include <asm/div64.h>
#include <asm/cpu.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/prom.h>
-#include <asm/mips-boards/maltaint.h>
-#include <asm/mc146818-time.h>
-
-unsigned long cpu_khz;
-#if defined(CONFIG_MIPS_ATLAS)
-static char display_string[] = " LINUX ON ATLAS ";
-#endif
-#if defined(CONFIG_MIPS_MALTA)
-#if defined(CONFIG_MIPS_MT_SMTC)
-static char display_string[] = " SMTC LINUX ON MALTA ";
-#else
-static char display_string[] = " LINUX ON MALTA ";
-#endif /* CONFIG_MIPS_MT_SMTC */
+#ifdef CONFIG_MIPS_MALTA
+#include <asm/mips-boards/maltaint.h>
#endif
-#if defined(CONFIG_MIPS_SEAD)
-static char display_string[] = " LINUX ON SEAD ";
+#ifdef CONFIG_MIPS_SEAD
+#include <asm/mips-boards/seadint.h>
#endif
-static unsigned int display_count;
-#define MAX_DISPLAY_COUNT (sizeof(display_string) - 8)
-#define CPUCTR_IMASKBIT (0x100 << MIPSCPU_INT_CPUCTR)
+unsigned long cpu_khz;
-static unsigned int timer_tick_count;
static int mips_cpu_timer_irq;
-extern void smtc_timer_broadcast(int);
+static int mips_cpu_perf_irq;
+extern int cp0_perfcount_irq;
-static inline void scroll_display_message(void)
+static void mips_timer_dispatch(void)
{
- if ((timer_tick_count++ % HZ) == 0) {
- mips_display_message(&display_string[display_count++]);
- if (display_count == MAX_DISPLAY_COUNT)
- display_count = 0;
- }
+ do_IRQ(mips_cpu_timer_irq);
}
-static void mips_timer_dispatch (struct pt_regs *regs)
+static void mips_perf_dispatch(void)
{
- do_IRQ (mips_cpu_timer_irq, regs);
+ do_IRQ(mips_cpu_perf_irq);
}
/*
- * Redeclare until I get around mopping the timer code insanity on MIPS.
- */
-extern int null_perf_irq(struct pt_regs *regs);
-
-extern int (*perf_irq)(struct pt_regs *regs);
-
-irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
-{
- int cpu = smp_processor_id();
- int r2 = cpu_has_mips_r2;
-
-#ifdef CONFIG_MIPS_MT_SMTC
- /*
- * In an SMTC system, one Count/Compare set exists per VPE.
- * Which TC within a VPE gets the interrupt is essentially
- * random - we only know that it shouldn't be one with
- * IXMT set. Whichever TC gets the interrupt needs to
- * send special interprocessor interrupts to the other
- * TCs to make sure that they schedule, etc.
- *
- * That code is specific to the SMTC kernel, not to
- * the a particular platform, so it's invoked from
- * the general MIPS timer_interrupt routine.
- */
-
- /*
- * DVPE is necessary so long as cross-VPE interrupts
- * are done via read-modify-write of Cause register.
- */
- int vpflags = dvpe();
- write_c0_compare (read_c0_count() - 1);
- clear_c0_cause(CPUCTR_IMASKBIT);
- evpe(vpflags);
-
- if (cpu_data[cpu].vpe_id == 0) {
- timer_interrupt(irq, dev_id, regs);
- scroll_display_message();
- } else
- write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
- smtc_timer_broadcast(cpu_data[cpu].vpe_id);
-
- if (cpu != 0)
- /*
- * Other CPUs should do profiling and process accounting
- */
- local_timer_interrupt(irq, dev_id, regs);
-
-#else /* CONFIG_MIPS_MT_SMTC */
- if (cpu == 0) {
- /*
- * CPU 0 handles the global timer interrupt job and process
- * accounting resets count/compare registers to trigger next
- * timer int.
- */
- if (!r2 || (read_c0_cause() & (1 << 26)))
- if (perf_irq(regs))
- goto out;
-
- /* we keep interrupt disabled all the time */
- if (!r2 || (read_c0_cause() & (1 << 30)))
- timer_interrupt(irq, NULL, regs);
-
- scroll_display_message();
- } else {
- /* Everyone else needs to reset the timer int here as
- ll_local_timer_interrupt doesn't */
- /*
- * FIXME: need to cope with counter underflow.
- * More support needs to be added to kernel/time for
- * counter/timer interrupts on multiple CPU's
- */
- write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
-
- /*
- * Other CPUs should do profiling and process accounting
- */
- local_timer_interrupt(irq, dev_id, regs);
- }
-#endif /* CONFIG_MIPS_MT_SMTC */
-
-out:
- return IRQ_HANDLED;
-}
-
-/*
- * Estimate CPU frequency. Sets mips_counter_frequency as a side-effect
+ * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
*/
static unsigned int __init estimate_cpu_frequency(void)
{
else
count = 6000000;
#endif
-#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
- unsigned int flags;
+#ifdef CONFIG_MIPS_MALTA
+ unsigned long flags;
+ unsigned int start;
local_irq_save(flags);
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
/* Start r4k counter. */
- write_c0_count(0);
+ start = read_c0_count();
/* Read counter exactly on falling edge of update flag */
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
- count = read_c0_count();
+ count = read_c0_count() - start;
/* restore interrupts */
local_irq_restore(flags);
return count;
}
-unsigned long __init mips_rtc_get_time(void)
+unsigned long read_persistent_clock(void)
{
return mc146818_get_cmos_time();
}
-void __init mips_time_init(void)
+static void __init plat_perf_setup(void)
+{
+#ifdef MSC01E_INT_BASE
+ if (cpu_has_veic) {
+ set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
+ mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
+ } else
+#endif
+ if (cp0_perfcount_irq >= 0) {
+ if (cpu_has_vint)
+ set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
+ mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
+#ifdef CONFIG_SMP
+ set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq);
+#endif
+ }
+}
+
+unsigned int __cpuinit get_c0_compare_int(void)
{
- unsigned int est_freq, flags;
+#ifdef MSC01E_INT_BASE
+ if (cpu_has_veic) {
+ set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
+ mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
+ } else
+#endif
+ {
+ if (cpu_has_vint)
+ set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
+ mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
+ }
- local_irq_save(flags);
+ return mips_cpu_timer_irq;
+}
+
+void __init plat_time_init(void)
+{
+ unsigned int est_freq;
/* Set Data mode - binary. */
CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
- est_freq = estimate_cpu_frequency ();
+ est_freq = estimate_cpu_frequency();
printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
(est_freq%1000000)*100/1000000);
cpu_khz = est_freq / 1000;
- local_irq_restore(flags);
-}
-
-void __init mips_timer_setup(struct irqaction *irq)
-{
- if (cpu_has_veic) {
- set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
- mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
- }
- else {
- if (cpu_has_vint)
- set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch);
- mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR;
- }
-
-
- /* we are using the cpu counter for timer interrupts */
- irq->handler = mips_timer_interrupt; /* we use our own handler */
-#ifdef CONFIG_MIPS_MT_SMTC
- setup_irq_smtc(mips_cpu_timer_irq, irq, CPUCTR_IMASKBIT);
-#else
- setup_irq(mips_cpu_timer_irq, irq);
-#endif /* CONFIG_MIPS_MT_SMTC */
-
-#ifdef CONFIG_SMP
- /* irq_desc(riptor) is a global resource, when the interrupt overlaps
- on seperate cpu's the first one tries to handle the second interrupt.
- The effect is that the int remains disabled on the second cpu.
- Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
- irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
+ mips_scroll_message();
+#ifdef CONFIG_I8253 /* Only Malta has a PIT */
+ setup_pit_timer();
#endif
- /* to generate the first timer interrupt */
- write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
+ plat_perf_setup();
}
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff