MIPS: Read watch registers with interrupts disabled.

[safe/jmp/linux-2.6] / arch / mips / kernel / r4k_switch.S

diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index d5c8b82..d9bfae5 100644 (file)
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -85,7 +85,7 @@
        move    $28, a2
        cpu_restore_nonscratch a1
 
-       PTR_ADDIU       t0, $28, _THREAD_SIZE - 32
+       PTR_ADDU        t0, $28, _THREAD_SIZE - 32
        set_saved_sp    t0, t1, t2
 #ifdef CONFIG_MIPS_MT_SMTC
        /* Read-modify-writes of Status must be atomic on a VPE */
@@ -169,7 +169,7 @@ LEAF(_init_fpu)
        or      t0, t1
        mtc0    t0, CP0_STATUS
 #endif /* CONFIG_MIPS_MT_SMTC */
-       fpu_enable_hazard
+       enable_fpu_hazard
 
        li      t1, FPU_DEFAULT
        ctc1    t1, fcr31