sh: convert /proc/cpu/aligmnent, /proc/cpu/kernel_alignment to seq_file

[safe/jmp/linux-2.6] / arch / mips / kernel / mips-mt.c

diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c
index 1a7d892..b2259e7 100644 (file)
--- a/arch/mips/kernel/mips-mt.c
+++ b/arch/mips/kernel/mips-mt.c
@@ -16,11 +16,32 @@
 #include <asm/system.h>
 #include <asm/hardirq.h>
 #include <asm/mmu_context.h>
-#include <asm/smp.h>
 #include <asm/mipsmtregs.h>
 #include <asm/r4kcache.h>
 #include <asm/cacheflush.h>
 
+int vpelimit;
+
+static int __init maxvpes(char *str)
+{
+       get_option(&str, &vpelimit);
+
+       return 1;
+}
+
+__setup("maxvpes=", maxvpes);
+
+int tclimit;
+
+static int __init maxtcs(char *str)
+{
+       get_option(&str, &tclimit);
+
+       return 1;
+}
+
+__setup("maxtcs=", maxtcs);
+
 /*
  * Dump new MIPS MT state for the core. Does not leave TCs halted.
  * Takes an argument which taken to be a pre-call MVPControl value.
@@ -62,8 +83,9 @@ void mips_mt_regdump(unsigned long mvpctl)
                                       read_vpe_c0_vpeconf0());
                                printk("   VPE%d.Status : %08lx\n",
                                       i, read_vpe_c0_status());
-                               printk("   VPE%d.EPC : %08lx\n",
-                                      i, read_vpe_c0_epc());
+                               printk("   VPE%d.EPC : %08lx %pS\n",
+                                      i, read_vpe_c0_epc(),
+                                      (void *) read_vpe_c0_epc());
                                printk("   VPE%d.Cause : %08lx\n",
                                       i, read_vpe_c0_cause());
                                printk("   VPE%d.Config7 : %08lx\n",
@@ -88,7 +110,8 @@ void mips_mt_regdump(unsigned long mvpctl)
                }
                printk("   TCStatus : %08lx\n", tcstatval);
                printk("   TCBind : %08lx\n", read_tc_c0_tcbind());
-               printk("   TCRestart : %08lx\n", read_tc_c0_tcrestart());
+               printk("   TCRestart : %08lx %pS\n",
+                      read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart());
                printk("   TCHalt : %08lx\n", haltval);
                printk("   TCContext : %08lx\n", read_tc_c0_tccontext());
                if (!haltval)
@@ -102,10 +125,10 @@ void mips_mt_regdump(unsigned long mvpctl)
        local_irq_restore(flags);
 }
 
-static int mt_opt_norps = 0;
+static int mt_opt_norps;
 static int mt_opt_rpsctl = -1;
 static int mt_opt_nblsu = -1;
-static int mt_opt_forceconfig7 = 0;
+static int mt_opt_forceconfig7;
 static int mt_opt_config7 = -1;
 
 static int __init rps_disable(char *s)
@@ -138,8 +161,8 @@ static int __init config7_set(char *str)
 __setup("config7=", config7_set);
 
 /* Experimental cache flush control parameters that should go away some day */
-int mt_protiflush = 0;
-int mt_protdflush = 0;
+int mt_protiflush;
+int mt_protdflush;
 int mt_n_iflushes = 1;
 int mt_n_dflushes = 1;
 
@@ -171,7 +194,7 @@ static int __init ndflush(char *s)
 }
 __setup("ndflush=", ndflush);
 
-static unsigned int itc_base = 0;
+static unsigned int itc_base;
 
 static int __init set_itc_base(char *str)
 {
@@ -211,7 +234,7 @@ void mips_mt_set_cpuoptions(void)
        if (oconfig7 != nconfig7) {
                __asm__ __volatile("sync");
                write_c0_config7(nconfig7);
-               ehb ();
+               ehb();
                printk("Config7: 0x%08x\n", read_c0_config7());
        }