MIPS: BCM63xx: Register SSB SPROM fallback in board's first stage callback

[safe/jmp/linux-2.6] / arch / mips / kernel / cpu-probe.c

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b13b8eb..be5bb16 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -14,7 +14,9 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/ptrace.h>
+#include <linux/smp.h>
 #include <linux/stddef.h>
+#include <linux/module.h>
 
 #include <asm/bugs.h>
 #include <asm/cpu.h>
@@ -22,7 +24,7 @@
 #include <asm/mipsregs.h>
 #include <asm/system.h>
 #include <asm/watch.h>
-
+#include <asm/spram.h>
 /*
  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  * the implementation of the "wait" feature differs between CPU families. This
@@ -30,7 +32,8 @@
  * The wait instruction stops the pipeline and reduces the power consumption of
  * the CPU very much.
  */
-void (*cpu_wait)(void) = NULL;
+void (*cpu_wait)(void);
+EXPORT_SYMBOL(cpu_wait);
 
 static void r3081_wait(void)
 {
@@ -90,16 +93,13 @@ static void rm7k_wait_irqoff(void)
        local_irq_enable();
 }
 
-/* The Au1xxx wait is available only if using 32khz counter or
- * external timer source, but specifically not CP0 Counter. */
-int allow_au1k_wait;
-
+/*
+ * The Au1xxx wait is available only if using 32khz counter or
+ * external timer source, but specifically not CP0 Counter.
+ * alchemy/common/time.c may override cpu_wait!
+ */
 static void au1k_wait(void)
 {
-       if (!allow_au1k_wait)
-               return;
-
-       /* using the wait instruction makes CP0 counter unusable */
        __asm__("       .set    mips3                   \n"
                "       cache   0x14, 0(%0)             \n"
                "       cache   0x14, 32(%0)            \n"
@@ -114,7 +114,7 @@ static void au1k_wait(void)
                : : "r" (au1k_wait));
 }
 
-static int __initdata nowait = 0;
+static int __initdata nowait;
 
 static int __init wait_disable(char *s)
 {
@@ -158,7 +158,11 @@ void __init check_wait(void)
        case CPU_25KF:
        case CPU_PR4450:
        case CPU_BCM3302:
+       case CPU_BCM6338:
+       case CPU_BCM6348:
+       case CPU_BCM6358:
        case CPU_CAVIUM_OCTEON:
+       case CPU_CAVIUM_OCTEON_PLUS:
                cpu_wait = r4k_wait;
                break;
 
@@ -281,6 +285,15 @@ static inline int __cpu_has_fpu(void)
        return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 }
 
+static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
+{
+#ifdef __NEED_VMBITS_PROBE
+       write_c0_entryhi(0x3fffffffffffe000ULL);
+       back_to_back_c0_hazard();
+       c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
+#endif
+}
+
 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
                | MIPS_CPU_COUNTER)
 
@@ -688,6 +701,19 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
        return config3 & MIPS_CONF_M;
 }
 
+static inline unsigned int decode_config4(struct cpuinfo_mips *c)
+{
+       unsigned int config4;
+
+       config4 = read_c0_config4();
+
+       if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
+           && cpu_has_tlb)
+               c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
+
+       return config4 & MIPS_CONF_M;
+}
+
 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
 {
        int ok;
@@ -706,16 +732,12 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
                ok = decode_config2(c);
        if (ok)
                ok = decode_config3(c);
+       if (ok)
+               ok = decode_config4(c);
 
        mips_probe_watch_registers(c);
 }
 
-#ifdef CONFIG_CPU_MIPSR2
-extern void spram_config(void);
-#else
-static inline void spram_config(void) {}
-#endif
-
 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 {
        decode_configs(c);
@@ -725,9 +747,6 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
                __cpu_name[cpu] = "MIPS 4Kc";
                break;
        case PRID_IMP_4KEC:
-               c->cputype = CPU_4KEC;
-               __cpu_name[cpu] = "MIPS 4KEc";
-               break;
        case PRID_IMP_4KECR2:
                c->cputype = CPU_4KEC;
                __cpu_name[cpu] = "MIPS 4KEc";
@@ -856,6 +875,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
        decode_configs(c);
        switch (c->processor_id & 0xff00) {
        case PRID_IMP_BCM3302:
+        /* same as PRID_IMP_BCM6338 */
                c->cputype = CPU_BCM3302;
                __cpu_name[cpu] = "Broadcom BCM3302";
                break;
@@ -863,6 +883,25 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
                c->cputype = CPU_BCM4710;
                __cpu_name[cpu] = "Broadcom BCM4710";
                break;
+       case PRID_IMP_BCM6345:
+               c->cputype = CPU_BCM6345;
+               __cpu_name[cpu] = "Broadcom BCM6345";
+               break;
+       case PRID_IMP_BCM6348:
+               c->cputype = CPU_BCM6348;
+               __cpu_name[cpu] = "Broadcom BCM6348";
+               break;
+       case PRID_IMP_BCM4350:
+               switch (c->processor_id & 0xf0) {
+               case PRID_REV_BCM6358:
+                       c->cputype = CPU_BCM6358;
+                       __cpu_name[cpu] = "Broadcom BCM6358";
+                       break;
+               default:
+                       c->cputype = CPU_UNKNOWN;
+                       break;
+               }
+               break;
        }
 }
 
@@ -873,12 +912,18 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
        case PRID_IMP_CAVIUM_CN38XX:
        case PRID_IMP_CAVIUM_CN31XX:
        case PRID_IMP_CAVIUM_CN30XX:
+               c->cputype = CPU_CAVIUM_OCTEON;
+               __cpu_name[cpu] = "Cavium Octeon";
+               goto platform;
        case PRID_IMP_CAVIUM_CN58XX:
        case PRID_IMP_CAVIUM_CN56XX:
        case PRID_IMP_CAVIUM_CN50XX:
        case PRID_IMP_CAVIUM_CN52XX:
-               c->cputype = CPU_CAVIUM_OCTEON;
-               __cpu_name[cpu] = "Cavium Octeon";
+               c->cputype = CPU_CAVIUM_OCTEON_PLUS;
+               __cpu_name[cpu] = "Cavium Octeon+";
+platform:
+               if (cpu == 0)
+                       __elf_platform = "octeon";
                break;
        default:
                printk(KERN_INFO "Unknown Octeon chip!\n");
@@ -888,6 +933,7 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
 }
 
 const char *__cpu_name[NR_CPUS];
+const char *__elf_platform;
 
 __cpuinit void cpu_probe(void)
 {
@@ -952,6 +998,8 @@ __cpuinit void cpu_probe(void)
                c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
        else
                c->srsets = 1;
+
+       cpu_probe_vmbits(c);
 }
 
 __cpuinit void cpu_report(void)