menu "Machine selection"
+config ZONE_DMA
+ bool
+
choice
prompt "System type"
default SGI_IP22
-config MIPS_MTX1
- bool "4G Systems MTX-1 board"
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select SOC_AU1500
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_SUPPORTS_LITTLE_ENDIAN
-
-config MIPS_BOSPORUS
- bool "AMD Alchemy Bosporus board"
- select SOC_AU1500
- select DMA_NONCOHERENT
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_SUPPORTS_LITTLE_ENDIAN
-
-config MIPS_PB1000
- bool "AMD Alchemy PB1000 board"
- select SOC_AU1000
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select SWAP_IO_SPACE
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_SUPPORTS_LITTLE_ENDIAN
-
-config MIPS_PB1100
- bool "AMD Alchemy PB1100 board"
- select SOC_AU1100
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select SWAP_IO_SPACE
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_SUPPORTS_LITTLE_ENDIAN
-
-config MIPS_PB1500
- bool "AMD Alchemy PB1500 board"
- select SOC_AU1500
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_SUPPORTS_LITTLE_ENDIAN
-
-config MIPS_PB1550
- bool "AMD Alchemy PB1550 board"
- select SOC_AU1550
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select MIPS_DISABLE_OBSOLETE_IDE
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_SUPPORTS_LITTLE_ENDIAN
-
-config MIPS_PB1200
- bool "AMD Alchemy PB1200 board"
- select SOC_AU1200
- select DMA_NONCOHERENT
- select MIPS_DISABLE_OBSOLETE_IDE
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_SUPPORTS_LITTLE_ENDIAN
-
-config MIPS_DB1000
- bool "AMD Alchemy DB1000 board"
- select SOC_AU1000
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_SUPPORTS_LITTLE_ENDIAN
-
-config MIPS_DB1100
- bool "AMD Alchemy DB1100 board"
- select SOC_AU1100
- select DMA_NONCOHERENT
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_SUPPORTS_LITTLE_ENDIAN
-
-config MIPS_DB1500
- bool "AMD Alchemy DB1500 board"
- select SOC_AU1500
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select MIPS_DISABLE_OBSOLETE_IDE
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_LITTLE_ENDIAN
-
-config MIPS_DB1550
- bool "AMD Alchemy DB1550 board"
- select SOC_AU1550
- select HW_HAS_PCI
- select DMA_NONCOHERENT
- select MIPS_DISABLE_OBSOLETE_IDE
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_SUPPORTS_LITTLE_ENDIAN
-
-config MIPS_DB1200
- bool "AMD Alchemy DB1200 board"
- select SOC_AU1200
- select DMA_COHERENT
- select MIPS_DISABLE_OBSOLETE_IDE
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_SUPPORTS_LITTLE_ENDIAN
-
-config MIPS_MIRAGE
- bool "AMD Alchemy Mirage board"
- select DMA_NONCOHERENT
- select SOC_AU1500
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_SUPPORTS_LITTLE_ENDIAN
+config MACH_ALCHEMY
+ bool "Alchemy processor based machines"
config BASLER_EXCITE
- bool "Basler eXcite smart camera support"
+ bool "Basler eXcite smart camera"
select DMA_COHERENT
select HW_HAS_PCI
select IRQ_CPU
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_KGDB
help
The eXcite is a smart camera platform manufactured by
- Basler Vision Technologies AG
+ Basler Vision Technologies AG.
config BASLER_EXCITE_PROTOTYPE
bool "Support for pre-release units"
select HW_HAS_PCI
select I8259
select IRQ_CPU
- select MIPS_GT64111
+ select PCI_GT64XXX_PCI0
select SYS_HAS_CPU_NEVADA
+ select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_LITTLE_ENDIAN
+ select GENERIC_HARDIRQS_NO__DO_IRQ
config MACH_DECSTATION
bool "DECstations"
select BOOT_ELF32
select DMA_NONCOHERENT
- select EARLY_PRINTK
+ select NO_IOPORT
select IRQ_CPU
select SYS_HAS_CPU_R3000
select SYS_HAS_CPU_R4X00
otherwise choose R3000.
-config MIPS_EV64120
- bool "Galileo EV64120 Evaluation board (EXPERIMENTAL)"
- depends on EXPERIMENTAL
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select MIPS_GT64120
- select SYS_HAS_CPU_R5000
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_64BIT_KERNEL
- select SYS_SUPPORTS_BIG_ENDIAN
- help
- This is an evaluation board based on the Galileo GT-64120
- single-chip system controller that contains a MIPS R5000 compatible
- core running at 75/100MHz. Their website is located at
- <http://www.marvell.com/>. Say Y here if you wish to build a
- kernel for this platform.
-
config MACH_JAZZ
bool "Jazz family of machines"
select ARC
select ARC32
select ARCH_MAY_HAVE_PC_FDC
select GENERIC_ISA_DMA
- select I8253
select I8259
select ISA
+ select PCSPEAKER
select SYS_HAS_CPU_R4X00
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_100HZ
+ select GENERIC_HARDIRQS_NO__DO_IRQ
help
This a family of machines based on the MIPS R4030 chipset which was
used by several vendors to build RISC/os and Windows NT workstations.
Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
Olivetti M700-10 workstations.
-config LASAT
- bool "LASAT Networks platforms"
+config LEMOTE_FULONG
+ bool "Lemote Fulong mini-PC"
+ select ARCH_SPARSEMEM_ENABLE
+ select SYS_HAS_CPU_LOONGSON2
select DMA_NONCOHERENT
+ select BOOT_ELF32
+ select BOARD_SCACHE
+ select HAVE_STD_PC_SERIAL_PORT
select HW_HAS_PCI
- select MIPS_GT64120
- select MIPS_NILE4
- select R5000_CPU_SCACHE
- select SYS_HAS_CPU_R5000
+ select I8259
+ select ISA
+ select IRQ_CPU
select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
+ select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_HAS_EARLY_PRINTK
+ select GENERIC_HARDIRQS_NO__DO_IRQ
+ select CPU_HAS_WB
+ help
+ Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and
+ an FPGA northbridge
config MIPS_ATLAS
bool "MIPS Atlas board"
select BOOT_ELF32
select DMA_NONCOHERENT
+ select SYS_HAS_EARLY_PRINTK
select IRQ_CPU
select HW_HAS_PCI
select MIPS_BOARDS_GEN
select MIPS_BONITO64
- select MIPS_GT64120
+ select PCI_GT64XXX_PCI0
select MIPS_MSC
select RM7000_CPU_SCACHE
select SWAP_IO_SPACE
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL
+ select SYS_SUPPORTS_SMARTMIPS
+ select GENERIC_HARDIRQS_NO__DO_IRQ
help
This enables support for the MIPS Technologies Atlas evaluation
board.
bool "MIPS Malta board"
select ARCH_MAY_HAVE_PC_FDC
select BOOT_ELF32
- select HAVE_STD_PC_SERIAL_PORT
select DMA_NONCOHERENT
select GENERIC_ISA_DMA
select IRQ_CPU
select MIPS_BOARDS_GEN
select MIPS_BONITO64
select MIPS_CPU_SCACHE
- select MIPS_GT64120
+ select PCI_GT64XXX_PCI0
select MIPS_MSC
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS64_R1
select SYS_HAS_CPU_NEVADA
select SYS_HAS_CPU_RM7000
+ select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_MULTITHREADING
+ select SYS_SUPPORTS_SMARTMIPS
help
This enables support for the MIPS Technologies Malta evaluation
board.
depends on EXPERIMENTAL
select IRQ_CPU
select DMA_NONCOHERENT
+ select SYS_HAS_EARLY_PRINTK
select MIPS_BOARDS_GEN
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SYS_SUPPORTS_SMARTMIPS
help
This enables support for the MIPS Technologies SEAD evaluation
board.
-config WR_PPMC
- bool "Wind River PPMC board"
- select IRQ_CPU
- select BOOT_ELF32
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select MIPS_GT64120
- select SWAP_IO_SPACE
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_HAS_CPU_MIPS32_R2
- select SYS_HAS_CPU_MIPS64_R1
- select SYS_HAS_CPU_NEVADA
- select SYS_HAS_CPU_RM7000
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_64BIT_KERNEL
- select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_LITTLE_ENDIAN
- help
- This enables support for the Wind River MIPS32 4KC PPMC evaluation
- board, which is based on GT64120 bridge chip.
-
config MIPS_SIM
bool 'MIPS simulator (MIPSsim)'
select DMA_NONCOHERENT
+ select SYS_HAS_EARLY_PRINTK
select IRQ_CPU
+ select BOOT_RAW
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
+ select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_MULTITHREADING
select SYS_SUPPORTS_LITTLE_ENDIAN
help
This option enables support for MIPS Technologies MIPSsim software
emulator.
-config MOMENCO_JAGUAR_ATX
- bool "Momentum Jaguar board"
- select BOOT_ELF32
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select IRQ_CPU
- select IRQ_CPU_RM7K
- select IRQ_MV64340
- select LIMITED_DMA
- select PCI_MARVELL
- select RM7000_CPU_SCACHE
- select SWAP_IO_SPACE
- select SYS_HAS_CPU_RM9000
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_64BIT_KERNEL
- select SYS_SUPPORTS_BIG_ENDIAN
- help
- The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by
- Momentum Computer <http://www.momenco.com/>.
-
-config MOMENCO_OCELOT
- bool "Momentum Ocelot board"
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select IRQ_CPU
- select IRQ_CPU_RM7K
- select MIPS_GT64120
- select RM7000_CPU_SCACHE
- select SWAP_IO_SPACE
- select SYS_HAS_CPU_RM7000
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_64BIT_KERNEL
- select SYS_SUPPORTS_BIG_ENDIAN
- help
- The Ocelot is a MIPS-based Single Board Computer (SBC) made by
- Momentum Computer <http://www.momenco.com/>.
-
-config MOMENCO_OCELOT_3
- bool "Momentum Ocelot-3 board"
- select BOOT_ELF32
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select IRQ_CPU
- select IRQ_CPU_RM7K
- select IRQ_MV64340
- select PCI_MARVELL
- select RM7000_CPU_SCACHE
- select SWAP_IO_SPACE
- select SYS_HAS_CPU_RM9000
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_64BIT_KERNEL
- select SYS_SUPPORTS_BIG_ENDIAN
- help
- The Ocelot-3 is based off Discovery III System Controller and
- PMC-Sierra Rm79000 core.
-
-config MOMENCO_OCELOT_C
- bool "Momentum Ocelot-C board"
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select IRQ_CPU
- select IRQ_MV64340
- select PCI_MARVELL
- select RM7000_CPU_SCACHE
- select SWAP_IO_SPACE
- select SYS_HAS_CPU_RM7000
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_64BIT_KERNEL
- select SYS_SUPPORTS_BIG_ENDIAN
- help
- The Ocelot is a MIPS-based Single Board Computer (SBC) made by
- Momentum Computer <http://www.momenco.com/>.
-
-config MOMENCO_OCELOT_G
- bool "Momentum Ocelot-G board"
+config MARKEINS
+ bool "NEC EMMA2RH Mark-eins"
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
- select IRQ_CPU_RM7K
- select PCI_MARVELL
- select RM7000_CPU_SCACHE
select SWAP_IO_SPACE
- select SYS_HAS_CPU_RM7000
select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SYS_HAS_CPU_R5000
help
- The Ocelot is a MIPS-based Single Board Computer (SBC) made by
- Momentum Computer <http://www.momenco.com/>.
+ This enables support for the R5432-based NEC Mark-eins
+ boards with R5500 CPU.
-config MIPS_XXS1500
- bool "MyCable XXS1500 board"
- select DMA_NONCOHERENT
- select SOC_AU1500
- select SYS_SUPPORTS_LITTLE_ENDIAN
+config MACH_VR41XX
+ bool "NEC VR4100 series based machines"
+ select SYS_HAS_CPU_VR41XX
+ select GENERIC_HARDIRQS_NO__DO_IRQ
-config PNX8550_V2PCI
- bool "Philips PNX8550 based Viper2-PCI board"
+config PNX8550_JBS
+ bool "Philips PNX8550 based JBS board"
select PNX8550
select SYS_SUPPORTS_LITTLE_ENDIAN
-config PNX8550_JBS
- bool "Philips PNX8550 based JBS board"
+config PNX8550_STB810
+ bool "Philips PNX8550 based STB810 board"
select PNX8550
select SYS_SUPPORTS_LITTLE_ENDIAN
-config DDB5477
- bool "NEC DDB Vrc-5477"
- select DDB5XXX_COMMON
+config PMC_MSP
+ bool "PMC-Sierra MSP chipsets"
+ depends on EXPERIMENTAL
select DMA_NONCOHERENT
- select HW_HAS_PCI
- select I8259
- select IRQ_CPU
- select SYS_HAS_CPU_R5432
+ select SWAP_IO_SPACE
+ select NO_EXCEPT_FILL
+ select BOOT_RAW
+ select SYS_HAS_CPU_MIPS32_R1
+ select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
- select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_KGDB
+ select IRQ_CPU
+ select SERIAL_8250
+ select SERIAL_8250_CONSOLE
help
- This enables support for the R5432-based NEC DDB Vrc-5477,
- or Rockhopper/SolutionGear boards with R5432/R5500 CPUs.
-
- Features : kernel debugging, serial terminal, NFS root fs, on-board
- ether port USB, AC97, PCI, etc.
-
-config MACH_VR41XX
- bool "NEC VR41XX-based machines"
- select SYS_HAS_CPU_VR41XX
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
+ This adds support for the PMC-Sierra family of Multi-Service
+ Processor System-On-A-Chips. These parts include a number
+ of integrated peripherals, interfaces and DSPs in addition to
+ a variety of MIPS cores.
config PMC_YOSEMITE
bool "PMC-Sierra Yosemite eval board"
select IRQ_CPU_RM9K
select SWAP_IO_SPACE
select SYS_HAS_CPU_RM9000
+ select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
+ select SYS_SUPPORTS_KGDB
select SYS_SUPPORTS_SMP
help
Yosemite is an evaluation board for the RM9000x2 processor
select DMA_COHERENT
select GENERIC_ISA_DMA
select HAVE_STD_PC_SERIAL_PORT
- select I8253
select I8259
select ISA
+ select PCSPEAKER
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
select ARCH_SPARSEMEM_ENABLE
+ select GENERIC_HARDIRQS_NO__DO_IRQ
+ select NR_CPUS_DEFAULT_1
+ select SYS_SUPPORTS_SMP
help
Qemu is a software emulator which among other architectures also
can simulate a MIPS32 4Kc system. This patch adds support for the
simulate actual MIPS hardware platforms. More information on Qemu
can be found at http://www.linux-mips.org/wiki/Qemu.
-config MARKEINS
- bool "Support for NEC EMMA2RH Mark-eins"
- select DMA_NONCOHERENT
- select HW_HAS_PCI
- select IRQ_CPU
- select SWAP_IO_SPACE
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_LITTLE_ENDIAN
- select SYS_HAS_CPU_R5000
- help
- This enables support for the R5432-based NEC Mark-eins
- boards with R5500 CPU.
-
config SGI_IP22
bool "SGI IP22 (Indy/Indigo2)"
select ARC
select SWAP_IO_SPACE
select SYS_HAS_CPU_R4X00
select SYS_HAS_CPU_R5000
+ select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select ARC64
select BOOT_ELF64
select DMA_IP27
- select EARLY_PRINTK
+ select SYS_HAS_EARLY_PRINTK
select HW_HAS_PCI
+ select NR_CPUS_DEFAULT_64
select PCI_DOMAINS
select SYS_HAS_CPU_R10000
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_KGDB
select SYS_SUPPORTS_NUMA
select SYS_SUPPORTS_SMP
+ select GENERIC_HARDIRQS_NO__DO_IRQ
help
This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
workstations. To compile a Linux kernel that runs on these, say Y
here.
config SGI_IP32
- bool "SGI IP32 (O2) (EXPERIMENTAL)"
- depends on EXPERIMENTAL
+ bool "SGI IP32 (O2)"
select ARC
select ARC32
select BOOT_ELF32
- select OWN_DMA
- select DMA_IP32
select DMA_NONCOHERENT
select HW_HAS_PCI
select R5000_CPU_SCACHE
help
If you want this kernel to run on SGI O2 workstation, say Y here.
-config SIBYTE_BIGSUR
- bool "Sibyte BCM91480B-BigSur"
+config SIBYTE_CRHINE
+ bool "Sibyte BCM91120C-CRhine"
+ depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
- select PCI_DOMAINS
- select SIBYTE_BCM1x80
+ select SIBYTE_BCM1120
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
-config SIBYTE_SWARM
- bool "Sibyte BCM91250A-SWARM"
+config SIBYTE_CARMEL
+ bool "Sibyte BCM91120x-Carmel"
+ depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
- select SIBYTE_SB1250
+ select SIBYTE_BCM1120
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
-config SIBYTE_SENTOSA
- bool "Sibyte BCM91250E-Sentosa"
+config SIBYTE_CRHONE
+ bool "Sibyte BCM91125C-CRhone"
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
- select SIBYTE_SB1250
+ select SIBYTE_BCM1125
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
config SIBYTE_RHONE
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
-config SIBYTE_CARMEL
- bool "Sibyte BCM91120x-Carmel"
- depends on EXPERIMENTAL
+config SIBYTE_SWARM
+ bool "Sibyte BCM91250A-SWARM"
select BOOT_ELF32
select DMA_COHERENT
- select SIBYTE_BCM1120
+ select NR_CPUS_DEFAULT_2
+ select SIBYTE_SB1250
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_SUPPORTS_KGDB
select SYS_SUPPORTS_LITTLE_ENDIAN
-config SIBYTE_PTSWARM
- bool "Sibyte BCM91250PT-PTSWARM"
+config SIBYTE_LITTLESUR
+ bool "Sibyte BCM91250C2-LittleSur"
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
+ select NR_CPUS_DEFAULT_2
select SIBYTE_SB1250
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
-config SIBYTE_LITTLESUR
- bool "Sibyte BCM91250C2-LittleSur"
+config SIBYTE_SENTOSA
+ bool "Sibyte BCM91250E-Sentosa"
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
+ select NR_CPUS_DEFAULT_2
select SIBYTE_SB1250
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
-config SIBYTE_CRHINE
- bool "Sibyte BCM91120C-CRhine"
+config SIBYTE_PTSWARM
+ bool "Sibyte BCM91250PT-PTSWARM"
depends on EXPERIMENTAL
select BOOT_ELF32
select DMA_COHERENT
- select SIBYTE_BCM1120
+ select NR_CPUS_DEFAULT_2
+ select SIBYTE_SB1250
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
-config SIBYTE_CRHONE
- bool "Sibyte BCM91125C-CRhone"
- depends on EXPERIMENTAL
+config SIBYTE_BIGSUR
+ bool "Sibyte BCM91480B-BigSur"
select BOOT_ELF32
select DMA_COHERENT
- select SIBYTE_BCM1125
+ select NR_CPUS_DEFAULT_4
+ select PCI_DOMAINS
+ select SIBYTE_BCM1x80
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
-config SNI_RM200_PCI
- bool "SNI RM200 PCI"
+config SNI_RM
+ bool "SNI RM200/300/400"
select ARC if CPU_LITTLE_ENDIAN
select ARC32 if CPU_LITTLE_ENDIAN
select ARCH_MAY_HAVE_PC_FDC
select BOOT_ELF32
select DMA_NONCOHERENT
select GENERIC_ISA_DMA
- select HAVE_STD_PC_SERIAL_PORT
select HW_HAS_EISA
select HW_HAS_PCI
- select I8253
+ select IRQ_CPU
select I8259
select ISA
+ select PCSPEAKER
select SWAP_IO_SPACE if CPU_BIG_ENDIAN
select SYS_HAS_CPU_R4X00
select SYS_HAS_CPU_R5000
+ select SYS_HAS_CPU_R10000
select R5000_CPU_SCACHE
+ select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
help
- The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens
- Nixdorf Informationssysteme (SNI), parent company of Pyramid
+ The SNI RM200/300/400 are MIPS-based machines manufactured by
+ Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
Technology and now in turn merged with Fujitsu. Say Y here to
support this machine type.
select SWAP_IO_SPACE
select SYS_HAS_CPU_TX39XX
select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_BIG_ENDIAN
- select TOSHIBA_BOARDS
+ select GENERIC_HARDIRQS_NO__DO_IRQ
config TOSHIBA_RBTX4927
- bool "Toshiba TBTX49[23]7 board"
+ bool "Toshiba RBTX49[23]7 board"
select DMA_NONCOHERENT
select HAS_TXX9_SERIAL
select HW_HAS_PCI
select I8259
- select ISA
select SWAP_IO_SPACE
select SYS_HAS_CPU_TX49XX
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_BIG_ENDIAN
- select TOSHIBA_BOARDS
+ select SYS_SUPPORTS_KGDB
+ select GENERIC_HARDIRQS_NO__DO_IRQ
help
This Toshiba board is based on the TX4927 processor. Say Y here to
support this machine type
select HAS_TXX9_SERIAL
select HW_HAS_PCI
select I8259
- select ISA
select SWAP_IO_SPACE
select SYS_HAS_CPU_TX49XX
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_BIG_ENDIAN
- select TOSHIBA_BOARDS
+ select SYS_SUPPORTS_KGDB
+ select GENERIC_HARDIRQS_NO__DO_IRQ
+ select GENERIC_GPIO
help
This Toshiba board is based on the TX4938 processor. Say Y here to
support this machine type
+config WR_PPMC
+ bool "Wind River PPMC board"
+ select IRQ_CPU
+ select BOOT_ELF32
+ select DMA_NONCOHERENT
+ select HW_HAS_PCI
+ select PCI_GT64XXX_PCI0
+ select SWAP_IO_SPACE
+ select SYS_HAS_CPU_MIPS32_R1
+ select SYS_HAS_CPU_MIPS32_R2
+ select SYS_HAS_CPU_MIPS64_R1
+ select SYS_HAS_CPU_NEVADA
+ select SYS_HAS_CPU_RM7000
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_64BIT_KERNEL
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ help
+ This enables support for the Wind River MIPS32 4KC PPMC evaluation
+ board, which is based on GT64120 bridge chip.
+
endchoice
-config KEXEC
- bool "Kexec system call (EXPERIMENTAL)"
- depends on EXPERIMENTAL
- help
- kexec is a system call that implements the ability to shutdown your
- current kernel, and to start another kernel. It is like a reboot
- but it is indepedent of the system firmware. And like a reboot
- you can start any kernel with it, not just Linux.
-
- The name comes from the similiarity to the exec system call.
-
- It is an ongoing process to be certain the hardware in a machine
- is properly shutdown, so do not be surprised if this code does not
- initially work for you. It may help to enable device hotplugging
- support. As of this writing the exact hardware interface is
- strongly in flux, so no good recommendation can be made.
-
-source "arch/mips/ddb5xxx/Kconfig"
-source "arch/mips/gt64120/ev64120/Kconfig"
+source "arch/mips/au1000/Kconfig"
source "arch/mips/jazz/Kconfig"
-source "arch/mips/lasat/Kconfig"
-source "arch/mips/momentum/Kconfig"
source "arch/mips/pmc-sierra/Kconfig"
source "arch/mips/sgi-ip27/Kconfig"
source "arch/mips/sibyte/Kconfig"
source "arch/mips/tx4927/Kconfig"
source "arch/mips/tx4938/Kconfig"
source "arch/mips/vr41xx/Kconfig"
-source "arch/mips/philips/pnx8550/common/Kconfig"
-source "arch/mips/cobalt/Kconfig"
endmenu
config RWSEM_XCHGADD_ALGORITHM
bool
+config ARCH_HAS_ILOG2_U32
+ bool
+ default n
+
+config ARCH_HAS_ILOG2_U64
+ bool
+ default n
+
config GENERIC_FIND_NEXT_BIT
bool
default y
bool
default y
+config GENERIC_HARDIRQS_NO__DO_IRQ
+ bool
+ default n
+
#
# Select some configuration options automatically based on user selections.
#
config ARCH_MAY_HAVE_PC_FDC
bool
+config BOOT_RAW
+ bool
+
config DMA_COHERENT
bool
config DMA_NEED_PCI_MAP_STATE
bool
-config OWN_DMA
- bool
-
config EARLY_PRINTK
+ bool "Early printk" if EMBEDDED && DEBUG_KERNEL
+ depends on SYS_HAS_EARLY_PRINTK
+ default y
+ help
+ This option enables special console drivers which allow the kernel
+ to print messages very early in the bootup process.
+
+ This is useful for kernel debugging when your machine crashes very
+ early before the console code is initialized. For normal operation,
+ it is not recommended because it looks ugly on some machines and
+ doesn't cooperate with an X server. You should normally say N here,
+ unless you want to debug such a crash.
+
+config SYS_HAS_EARLY_PRINTK
bool
config GENERIC_ISA_DMA
bool
+ select ZONE_DMA
config I8259
bool
-config LIMITED_DMA
- bool
- select HIGHMEM
- select SYS_SUPPORTS_HIGHMEM
-
config MIPS_BONITO64
bool
config MIPS_MSC
bool
-config MIPS_NILE4
- bool
-
config MIPS_DISABLE_OBSOLETE_IDE
bool
+config NO_IOPORT
+ def_bool n
+
config GENERIC_ISA_DMA_SUPPORT_BROKEN
bool
+ select ZONE_DMA
+
+config GENERIC_GPIO
+ bool
#
# Endianess selection. Sufficiently obscure so many users don't know what to
byte order. These modes require different kernels and a different
Linux distribution. In general there is one preferred byteorder for a
particular system but some systems are just as commonly used in the
- one or the other endianess.
+ one or the other endianness.
config CPU_BIG_ENDIAN
bool "Big endian"
endchoice
+config SYS_SUPPORTS_APM_EMULATION
+ bool
+
config SYS_SUPPORTS_BIG_ENDIAN
bool
config IRQ_CPU_RM9K
bool
-config IRQ_MV64340
+config IRQ_MSP_SLP
bool
-config DDB5XXX_COMMON
+config IRQ_MSP_CIC
bool
config MIPS_BOARDS_GEN
bool
-config MIPS_GT64111
+config PCI_GT64XXX_PCI0
bool
-config MIPS_GT64120
+config NO_EXCEPT_FILL
bool
config MIPS_TX3927
config MIPS_RM9122
bool
select SERIAL_RM9000
- select GPI_RM9000
- select WDT_RM9000
-
-config PCI_MARVELL
- bool
-
-config SOC_AU1000
- bool
- select SOC_AU1X00
-
-config SOC_AU1100
- bool
- select SOC_AU1X00
-
-config SOC_AU1500
- bool
- select SOC_AU1X00
-
-config SOC_AU1550
- bool
- select SOC_AU1X00
-
-config SOC_AU1200
- bool
- select SOC_AU1X00
-
-config SOC_AU1X00
- bool
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_SUPPORTS_32BIT_KERNEL
config PNX8550
bool
select DMA_NONCOHERENT
select HW_HAS_PCI
select SYS_HAS_CPU_MIPS32_R1
+ select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
+ select GENERIC_HARDIRQS_NO__DO_IRQ
+ select SYS_SUPPORTS_KGDB
+ select GENERIC_GPIO
config SWAP_IO_SPACE
bool
config SERIAL_RM9000
bool
-config GPI_RM9000
- bool
-
-config WDT_RM9000
- bool
-
#
# Unfortunately not all GT64120 systems run the chip at the same clock.
# As the user for the clock rate and try to minimize the available options.
#
choice
prompt "Galileo Chip Clock"
- #default SYSCLK_83 if MIPS_EV64120
- depends on MIPS_EV64120 || MOMENCO_OCELOT || MOMENCO_OCELOT_G
- default SYSCLK_83 if MIPS_EV64120
- default SYSCLK_100 if MOMENCO_OCELOT || MOMENCO_OCELOT_G
-
-config SYSCLK_75
- bool "75" if MIPS_EV64120
-
-config SYSCLK_83
- bool "83.3" if MIPS_EV64120
+ depends on MOMENCO_OCELOT
+ default SYSCLK_100 if MOMENCO_OCELOT
config SYSCLK_100
- bool "100" if MIPS_EV64120 || MOMENCO_OCELOT || MOMENCO_OCELOT_G
+ bool "100" if MOMENCO_OCELOT
endchoice
config MIPS_L1_CACHE_SHIFT
int
default "4" if MACH_DECSTATION
- default "7" if SGI_IP27
+ default "7" if SGI_IP27 || SNI_RM
+ default "4" if PMC_MSP4200_EVAL
default "5"
config HAVE_STD_PC_SERIAL_PORT
config ARC_CONSOLE
bool "ARC console support"
- depends on SGI_IP22 || SNI_RM200_PCI
+ depends on SGI_IP22 || (SNI_RM && CPU_LITTLE_ENDIAN)
config ARC_MEMORY
bool
- depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP32
+ depends on MACH_JAZZ || SNI_RM || SGI_IP32
default y
config ARC_PROMLIB
bool
- depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP22 || SGI_IP32
+ depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP32
default y
config ARC64
config BOOT_ELF64
bool
-config TOSHIBA_BOARDS
- bool
-
menu "CPU selection"
choice
prompt "CPU type"
default CPU_R4X00
+config CPU_LOONGSON2
+ bool "Loongson 2"
+ depends on SYS_HAS_CPU_LOONGSON2
+ select CPU_SUPPORTS_32BIT_KERNEL
+ select CPU_SUPPORTS_64BIT_KERNEL
+ select CPU_SUPPORTS_HIGHMEM
+ help
+ The Loongson 2E processor implements the MIPS III instruction set
+ with many extensions.
+
config CPU_MIPS32_R1
bool "MIPS32 Release 1"
depends on SYS_HAS_CPU_MIPS32_R1
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
+ select WEAK_ORDERING
config CPU_SB1
bool "SB1"
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
+ select WEAK_ORDERING
endchoice
+config SYS_HAS_CPU_LOONGSON2
+ bool
+
config SYS_HAS_CPU_MIPS32_R1
bool
config SYS_HAS_CPU_SB1
bool
+#
+# CPU may reorder R->R, R->W, W->R, W->W
+# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
+#
+config WEAK_ORDERING
+ bool
+
+#
+# CPU may reorder reads and writes beyond LL/SC
+# CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
+#
+config WEAK_REORDERING_BEYOND_LLSC
+ bool
endmenu
#
bool "Use 1 TC on each available VPE for SMP"
depends on SYS_SUPPORTS_MULTITHREADING
select CPU_MIPSR2_IRQ_VI
+ select CPU_MIPSR2_IRQ_EI
select CPU_MIPSR2_SRS
select MIPS_MT
+ select NR_CPUS_DEFAULT_2
select SMP
select SYS_SUPPORTS_SMP
help
#depends on CPU_MIPS64_R2 # once there is hardware ...
depends on SYS_SUPPORTS_MULTITHREADING
select CPU_MIPSR2_IRQ_VI
+ select CPU_MIPSR2_IRQ_EI
select CPU_MIPSR2_SRS
select MIPS_MT
+ select NR_CPUS_DEFAULT_8
select SMP
select SYS_SUPPORTS_SMP
help
This is a kernel model which is known a SMTC or lately has been
marketesed into SMVP.
-config MIPS_VPE_LOADER
- bool "VPE loader support."
- depends on SYS_SUPPORTS_MULTITHREADING
- select MIPS_MT
- help
- Includes a loader for loading an elf relocatable object
- onto another VPE and running it.
-
endchoice
config MIPS_MT
config MIPS_MT_FPAFF
bool "Dynamic FPU affinity for FP-intensive threads"
- depends on MIPS_MT
default y
+ depends on MIPS_MT_SMP || MIPS_MT_SMTC
+
+config MIPS_VPE_LOADER
+ bool "VPE loader support."
+ depends on SYS_SUPPORTS_MULTITHREADING
+ select CPU_MIPSR2_IRQ_VI
+ select CPU_MIPSR2_IRQ_EI
+ select CPU_MIPSR2_SRS
+ select MIPS_MT
+ help
+ Includes a loader for loading an elf relocatable object
+ onto another VPE and running it.
+
+config MIPS_MT_SMTC_INSTANT_REPLAY
+ bool "Low-latency Dispatch of Deferred SMTC IPIs"
+ depends on MIPS_MT_SMTC && !PREEMPT
+ default y
+ help
+ SMTC pseudo-interrupts between TCs are deferred and queued
+ if the target TC is interrupt-inhibited (IXMT). In the first
+ SMTC prototypes, these queued IPIs were serviced on return
+ to user mode, or on entry into the kernel idle loop. The
+ INSTANT_REPLAY option dispatches them as part of local_irq_restore()
+ processing, which adds runtime overhead (hence the option to turn
+ it off), but ensures that IPIs are handled promptly even under
+ heavy I/O interrupt load.
+
+config MIPS_MT_SMTC_IM_BACKSTOP
+ bool "Use per-TC register bits as backstop for inhibited IM bits"
+ depends on MIPS_MT_SMTC
+ default y
+ help
+ To support multiple TC microthreads acting as "CPUs" within
+ a VPE, VPE-wide interrupt mask bits must be specially manipulated
+ during interrupt handling. To support legacy drivers and interrupt
+ controller management code, SMTC has a "backstop" to track and
+ if necessary restore the interrupt mask. This has some performance
+ impact on interrupt service overhead. Disable it only if you know
+ what you are doing.
config MIPS_VPE_LOADER_TOM
bool "Load VPE program into memory hidden from linux"
default y
config 64BIT_PHYS_ADDR
- bool "Support for 64-bit physical address space"
- depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && 32BIT
+ bool
config CPU_HAS_LLSC
bool
+config CPU_HAS_SMARTMIPS
+ depends on SYS_SUPPORTS_SMARTMIPS
+ bool "Support for the SmartMIPS ASE"
+ help
+ SmartMIPS is a extension of the MIPS32 architecture aimed at
+ increased security at both hardware and software level for
+ smartcards. Enabling this option will allow proper use of the
+ SmartMIPS instructions by Linux applications. However a kernel with
+ this option will not work on a MIPS core without SmartMIPS core. If
+ you don't know you probably don't have SmartMIPS and should say N
+ here.
+
config CPU_HAS_WB
bool
+config 64BIT_CONTEXT
+ bool "Save 64bit integer registers"
+ depends on 32BIT && CPU_LOONGSON2
+ help
+ Loongson2 CPU is 64bit , when used in 32BIT mode, its integer
+ registers can still be accessed as 64bit, mainly for multimedia
+ instructions. We must have all 64bit save/restored to make sure
+ those instructions to get correct result.
+
#
# Vectored interrupt mode is an R2 feature
#
config SYS_SUPPORTS_HIGHMEM
bool
+config SYS_SUPPORTS_SMARTMIPS
+ bool
+
config ARCH_FLATMEM_ENABLE
def_bool y
depends on !NUMA
bool
default y if SGI_IP27
help
- Say Y to upport efficient handling of discontiguous physical memory,
+ Say Y to support efficient handling of discontiguous physical memory,
for architectures which are either NUMA (Non-Uniform Memory Access)
or have huge holes in the physical address space for other reasons.
See <file:Documentation/vm/numa> for more.
config SYS_SUPPORTS_SMP
bool
+config NR_CPUS_DEFAULT_1
+ bool
+
+config NR_CPUS_DEFAULT_2
+ bool
+
+config NR_CPUS_DEFAULT_4
+ bool
+
+config NR_CPUS_DEFAULT_8
+ bool
+
+config NR_CPUS_DEFAULT_16
+ bool
+
+config NR_CPUS_DEFAULT_32
+ bool
+
+config NR_CPUS_DEFAULT_64
+ bool
+
config NR_CPUS
int "Maximum number of CPUs (2-64)"
- range 2 64
+ range 1 64 if NR_CPUS_DEFAULT_1
depends on SMP
- default "64" if SGI_IP27
- default "2"
- default "8" if MIPS_MT_SMTC
+ default "1" if NR_CPUS_DEFAULT_1
+ default "2" if NR_CPUS_DEFAULT_2
+ default "4" if NR_CPUS_DEFAULT_4
+ default "8" if NR_CPUS_DEFAULT_8
+ default "16" if NR_CPUS_DEFAULT_16
+ default "32" if NR_CPUS_DEFAULT_32
+ default "64" if NR_CPUS_DEFAULT_64
help
This allows you to specify the maximum number of CPUs which this
kernel will support. The maximum supported value is 32 for 32-bit
kernel and 64 for 64-bit kernels; the minimum value which makes
- sense is 2.
+ sense is 1 for Qemu (useful only for kernel debugging purposes)
+ and 2 for all others.
This is purely to save memory - each supported CPU adds
- approximately eight kilobytes to the kernel image.
+ approximately eight kilobytes to the kernel image. For best
+ performance should round up your number of processors to the next
+ power of two.
#
# Timer Interrupt Frequency Configuration
source "kernel/Kconfig.preempt"
-config RTC_DS1742
- bool "DS1742 BRAM/RTC support"
- depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927
-
config MIPS_INSANE_LARGE
bool "Support for large 64-bit configurations"
depends on CPU_R10000 && 64BIT
This will result in additional memory usage, so it is not
recommended for normal users.
+config KEXEC
+ bool "Kexec system call (EXPERIMENTAL)"
+ depends on EXPERIMENTAL
+ help
+ kexec is a system call that implements the ability to shutdown your
+ current kernel, and to start another kernel. It is like a reboot
+ but it is independent of the system firmware. And like a reboot
+ you can start any kernel with it, not just Linux.
+
+ The name comes from the similiarity to the exec system call.
+
+ It is an ongoing process to be certain the hardware in a machine
+ is properly shutdown, so do not be surprised if this code does not
+ initially work for you. It may help to enable device hotplugging
+ support. As of this writing the exact hardware interface is
+ strongly in flux, so no good recommendation can be made.
+
+config SECCOMP
+ bool "Enable seccomp to safely compute untrusted bytecode"
+ depends on PROC_FS
+ default y
+ help
+ This kernel feature is useful for number crunching applications
+ that may need to compute untrusted bytecode during their
+ execution. By using pipes or other transports made available to
+ the process as file descriptors supporting the read/write
+ syscalls, it's possible to isolate those applications in
+ their own address space using seccomp. Once seccomp is
+ enabled via /proc/<pid>/seccomp, it cannot be disabled
+ and the task is only allowed to execute a few safe syscalls
+ defined by each seccomp mode.
+
+ If unsure, say Y. Only embedded should say N here.
+
endmenu
config RWSEM_GENERIC_SPINLOCK
bool
default y
-config I8253
+config PCSPEAKER
bool
source "drivers/pcmcia/Kconfig"
depends on MIPS32_COMPAT
default y
+config SYSVIPC_COMPAT
+ bool
+ depends on COMPAT && SYSVIPC
+ default y
+
config MIPS32_O32
bool "Kernel support for o32 binaries"
depends on MIPS32_COMPAT
bool
default y if MIPS32_O32 || MIPS32_N32
-config SECCOMP
- bool "Enable seccomp to safely compute untrusted bytecode"
- depends on PROC_FS && BROKEN
- default y
- help
- This kernel feature is useful for number crunching applications
- that may need to compute untrusted bytecode during their
- execution. By using pipes or other transports made available to
- the process as file descriptors supporting the read/write
- syscalls, it's possible to isolate those applications in
- their own address space using seccomp. Once seccomp is
- enabled via /proc/<pid>/seccomp, it cannot be disabled
- and the task is only allowed to execute a few safe syscalls
- defined by each seccomp mode.
+endmenu
- If unsure, say Y. Only embedded should say N here.
+menu "Power management options"
-config PM
- bool "Power Management support (EXPERIMENTAL)"
- depends on EXPERIMENTAL && SOC_AU1X00
-
-config APM
- tristate "Advanced Power Management Emulation"
- depends on PM
- ---help---
- APM is a BIOS specification for saving power using several different
- techniques. This is mostly useful for battery powered systems with
- APM compliant BIOSes. If you say Y here, the system time will be
- reset after a RESUME operation, the /proc/apm device will provide
- battery status information, and user-space programs will receive
- notification of APM "events" (e.g. battery status change).
-
- In order to use APM, you will need supporting software. For location
- and more information, read <file:Documentation/pm.txt> and the
- Battery Powered Linux mini-HOWTO, available from
- <http://www.tldp.org/docs.html#howto>.
-
- This driver does not spin down disk drives (see the hdparm(8)
- manpage ("man 8 hdparm") for that), and it doesn't turn off
- VESA-compliant "green" monitors.
-
- Generally, if you don't have a battery in your machine, there isn't
- much point in using this driver and you should say N. If you get
- random kernel OOPSes or reboots that don't seem to be related to
- anything, try disabling/enabling this option (or disabling/enabling
- APM in your BIOS).
+source "kernel/power/Kconfig"
endmenu
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff