Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6

[safe/jmp/linux-2.6] / arch / microblaze / kernel / head.S

diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S
index e41c6ce..1bf7398 100644 (file)
--- a/arch/microblaze/kernel/head.S
+++ b/arch/microblaze/kernel/head.S
@@ -28,10 +28,11 @@
  * for more details.
  */
 
+#include <linux/init.h>
 #include <linux/linkage.h>
 #include <asm/thread_info.h>
 #include <asm/page.h>
-#include <asm/prom.h>          /* for OF_DT_HEADER */
+#include <linux/of_fdt.h>              /* for OF_DT_HEADER */
 
 #ifdef CONFIG_MMU
 #include <asm/setup.h> /* COMMAND_LINE_SIZE */
@@ -49,11 +50,27 @@ swapper_pg_dir:
 
 #endif /* CONFIG_MMU */
 
-       .text
+       __HEAD
 ENTRY(_start)
+#if CONFIG_KERNEL_BASE_ADDR == 0
+       brai    TOPHYS(real_start)
+       .org    0x100
+real_start:
+#endif
+
        mfs     r1, rmsr
        andi    r1, r1, ~2
        mts     rmsr, r1
+/*
+ * Here is checking mechanism which check if Microblaze has msr instructions
+ * We load msr and compare it with previous r1 value - if is the same,
+ * msr instructions works if not - cpu don't have them.
+ */
+       /* r8=0 - I have msr instr, 1 - I don't have them */
+       rsubi   r0, r0, 1       /* set the carry bit */
+       msrclr  r0, 0x4         /* try to clear it */
+       /* read the carry bit, r8 will be '0' if msrclr exists */
+       addik   r8, r0, 0
 
 /* r7 may point to an FDT, or there may be one linked in.
    if it's in r7, we've got to save it away ASAP.
@@ -89,8 +106,8 @@ no_fdt_arg:
        tophys(r4,r4)                   /* convert to phys address */
        ori     r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */
 _copy_command_line:
-       lbu     r7, r5, r6 /* r7=r5+r6 - r5 contain pointer to command line */
-       sb      r7, r4, r6              /* addr[r4+r6]= r7*/
+       lbu     r2, r5, r6 /* r2=r5+r6 - r5 contain pointer to command line */
+       sb      r2, r4, r6              /* addr[r4+r6]= r2*/
        addik   r6, r6, 1               /* increment counting */
        bgtid   r3, _copy_command_line  /* loop for all entries       */
        addik   r3, r3, -1              /* descrement loop */
@@ -118,7 +135,7 @@ _copy_bram:
         * virtual to physical.
         */
        nop
-       addik   r3, r0, 63              /* Invalidate all TLB entries */
+       addik   r3, r0, MICROBLAZE_TLB_SIZE -1  /* Invalidate all TLB entries */
 _invalidate:
        mts     rtlbx, r3
        mts     rtlbhi, r0                      /* flush: ensure V is clear   */
@@ -126,6 +143,11 @@ _invalidate:
        addik   r3, r3, -1
        /* sync */
 
+       /* Setup the kernel PID */
+       mts     rpid,r0                 /* Load the kernel PID */
+       nop
+       bri     4
+
        /*
         * We should still be executing code at physical address area
         * RAM_BASEADDR at this point. However, kernel code is at
@@ -136,10 +158,6 @@ _invalidate:
        addik   r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */
        tophys(r4,r3)                   /* Load the kernel physical address */
 
-       mts     rpid,r0                 /* Load the kernel PID */
-       nop
-       bri     4
-
        /*
         * Configure and load two entries into TLB slots 0 and 1.
         * In case we are pinning TLBs, these are reserved in by the
@@ -209,8 +227,8 @@ start_here:
         * Please see $(ARCH)/mach-$(SUBARCH)/setup.c for
         * the function.
         */
-       la      r8, r0, machine_early_init
-       brald   r15, r8
+       la      r9, r0, machine_early_init
+       brald   r15, r9
        nop
 
 #ifndef CONFIG_MMU