Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[safe/jmp/linux-2.6] / arch / ia64 / pci / pci.c
index 276512f..211fcfd 100644 (file)
@@ -18,7 +18,6 @@
 #include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/slab.h>
-#include <linux/smp_lock.h>
 #include <linux/spinlock.h>
 
 #include <asm/machvec.h>
@@ -44,8 +43,7 @@
 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg)      \
        (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
 
-static int
-pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn,
+int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn,
              int reg, int len, u32 *value)
 {
        u64 addr, data = 0;
@@ -69,8 +67,7 @@ pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn,
        return 0;
 }
 
-static int
-pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn,
+int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn,
               int reg, int len, u32 value)
 {
        u64 addr;
@@ -92,24 +89,17 @@ pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn,
        return 0;
 }
 
-static struct pci_raw_ops pci_sal_ops = {
-       .read =         pci_sal_read,
-       .write =        pci_sal_write
-};
-
-struct pci_raw_ops *raw_pci_ops = &pci_sal_ops;
-
-static int
-pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
+static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+                                                       int size, u32 *value)
 {
-       return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
+       return raw_pci_read(pci_domain_nr(bus), bus->number,
                                 devfn, where, size, value);
 }
 
-static int
-pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
+static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
+                                                       int size, u32 value)
 {
-       return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
+       return raw_pci_write(pci_domain_nr(bus), bus->number,
                                  devfn, where, size, value);
 }
 
@@ -125,11 +115,10 @@ alloc_pci_controller (int seg)
 {
        struct pci_controller *controller;
 
-       controller = kmalloc(sizeof(*controller), GFP_KERNEL);
+       controller = kzalloc(sizeof(*controller), GFP_KERNEL);
        if (!controller)
                return NULL;
 
-       memset(controller, 0, sizeof(*controller));
        controller->segment = seg;
        controller->node = -1;
        return controller;
@@ -335,7 +324,6 @@ pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
 struct pci_bus * __devinit
 pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
 {
-       struct pci_root_info info;
        struct pci_controller *controller;
        unsigned int windows = 0;
        struct pci_bus *pbus;
@@ -356,21 +344,31 @@ pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
 
        acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
                        &windows);
-       controller->window = kmalloc_node(sizeof(*controller->window) * windows,
-                       GFP_KERNEL, controller->node);
-       if (!controller->window)
-               goto out2;
-
-       name = kmalloc(16, GFP_KERNEL);
-       if (!name)
-               goto out3;
-
-       sprintf(name, "PCI Bus %04x:%02x", domain, bus);
-       info.controller = controller;
-       info.name = name;
-       acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window,
-                       &info);
-
+       if (windows) {
+               struct pci_root_info info;
+
+               controller->window =
+                       kmalloc_node(sizeof(*controller->window) * windows,
+                                    GFP_KERNEL, controller->node);
+               if (!controller->window)
+                       goto out2;
+
+               name = kmalloc(16, GFP_KERNEL);
+               if (!name)
+                       goto out3;
+
+               sprintf(name, "PCI Bus %04x:%02x", domain, bus);
+               info.controller = controller;
+               info.name = name;
+               acpi_walk_resources(device->handle, METHOD_NAME__CRS,
+                       add_window, &info);
+       }
+       /*
+        * See arch/x86/pci/acpi.c.
+        * The desired pci bus might already be scanned in a quirk. We
+        * should handle the case here, but it appears that IA64 hasn't
+        * such quirk. So we just ignore the case now.
+        */
        pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller);
        if (pbus)
                pcibios_setup_root_windows(pbus, controller);
@@ -469,10 +467,11 @@ pcibios_fixup_resources(struct pci_dev *dev, int start, int limit)
        }
 }
 
-static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
+void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
 {
        pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES);
 }
+EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources);
 
 static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev)
 {
@@ -493,6 +492,7 @@ pcibios_fixup_bus (struct pci_bus *b)
        }
        list_for_each_entry(dev, &b->devices, bus_list)
                pcibios_fixup_device_resources(dev);
+       platform_pci_fixup_bus(b);
 
        return;
 }
@@ -505,64 +505,26 @@ pcibios_update_irq (struct pci_dev *dev, int irq)
        /* ??? FIXME -- record old value for shutdown.  */
 }
 
-static inline int
-pcibios_enable_resources (struct pci_dev *dev, int mask)
-{
-       u16 cmd, old_cmd;
-       int idx;
-       struct resource *r;
-       unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM;
-
-       if (!dev)
-               return -EINVAL;
-
-       pci_read_config_word(dev, PCI_COMMAND, &cmd);
-       old_cmd = cmd;
-       for (idx=0; idx<PCI_NUM_RESOURCES; idx++) {
-               /* Only set up the desired resources.  */
-               if (!(mask & (1 << idx)))
-                       continue;
-
-               r = &dev->resource[idx];
-               if (!(r->flags & type_mask))
-                       continue;
-               if ((idx == PCI_ROM_RESOURCE) &&
-                               (!(r->flags & IORESOURCE_ROM_ENABLE)))
-                       continue;
-               if (!r->start && r->end) {
-                       printk(KERN_ERR
-                              "PCI: Device %s not available because of resource collisions\n",
-                              pci_name(dev));
-                       return -EINVAL;
-               }
-               if (r->flags & IORESOURCE_IO)
-                       cmd |= PCI_COMMAND_IO;
-               if (r->flags & IORESOURCE_MEM)
-                       cmd |= PCI_COMMAND_MEMORY;
-       }
-       if (cmd != old_cmd) {
-               printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
-               pci_write_config_word(dev, PCI_COMMAND, cmd);
-       }
-       return 0;
-}
-
 int
 pcibios_enable_device (struct pci_dev *dev, int mask)
 {
        int ret;
 
-       ret = pcibios_enable_resources(dev, mask);
+       ret = pci_enable_resources(dev, mask);
        if (ret < 0)
                return ret;
 
-       return acpi_pci_irq_enable(dev);
+       if (!dev->msi_enabled)
+               return acpi_pci_irq_enable(dev);
+       return 0;
 }
 
 void
 pcibios_disable_device (struct pci_dev *dev)
 {
-       acpi_pci_irq_disable(dev);
+       BUG_ON(atomic_read(&dev->enable_cnt));
+       if (!dev->msi_enabled)
+               acpi_pci_irq_disable(dev);
 }
 
 void
@@ -574,7 +536,7 @@ pcibios_align_resource (void *data, struct resource *res,
 /*
  * PCI BIOS setup, always defaults to SAL interface
  */
-char * __init
+char * __devinit
 pcibios_setup (char *str)
 {
        return str;
@@ -584,6 +546,9 @@ int
 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
                     enum pci_mmap_state mmap_state, int write_combine)
 {
+       unsigned long size = vma->vm_end - vma->vm_start;
+       pgprot_t prot;
+
        /*
         * I/O space cannot be accessed via normal processor loads and
         * stores on this platform.
@@ -597,15 +562,24 @@ pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
                 */
                return -EINVAL;
 
+       if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
+               return -EINVAL;
+
+       prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
+                                   vma->vm_page_prot);
+
        /*
-        * Leave vm_pgoff as-is, the PCI space address is the physical
-        * address on this platform.
+        * If the user requested WC, the kernel uses UC or WC for this region,
+        * and the chipset supports WC, we can use WC. Otherwise, we have to
+        * use the same attribute the kernel uses.
         */
-       if (write_combine && efi_range_is_wc(vma->vm_start,
-                                            vma->vm_end - vma->vm_start))
+       if (write_combine &&
+           ((pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_UC ||
+            (pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_WC) &&
+           efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start))
                vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
        else
-               vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+               vma->vm_page_prot = prot;
 
        if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
                             vma->vm_end - vma->vm_start, vma->vm_page_prot))
@@ -640,22 +614,25 @@ char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
  * vector to get the base address.
  */
 int
-pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma)
+pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma,
+                          enum pci_mmap_state mmap_state)
 {
        unsigned long size = vma->vm_end - vma->vm_start;
        pgprot_t prot;
        char *addr;
 
+       /* We only support mmap'ing of legacy memory space */
+       if (mmap_state != pci_mmap_mem)
+               return -ENOSYS;
+
        /*
         * Avoid attribute aliasing.  See Documentation/ia64/aliasing.txt
         * for more details.
         */
-       if (!valid_mmap_phys_addr_range(vma->vm_pgoff << PAGE_SHIFT, size))
+       if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
                return -EINVAL;
        prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
                                    vma->vm_page_prot);
-       if (pgprot_val(prot) != pgprot_val(pgprot_noncached(vma->vm_page_prot)))
-               return -EINVAL;
 
        addr = pci_get_legacy_mem(bus);
        if (IS_ERR(addr))
@@ -737,84 +714,44 @@ int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
        return ret;
 }
 
+/* It's defined in drivers/pci/pci.c */
+extern u8 pci_cache_line_size;
+
 /**
- * pci_cacheline_size - determine cacheline size for PCI devices
- * @dev: void
+ * set_pci_cacheline_size - determine cacheline size for PCI devices
  *
  * We want to use the line-size of the outer-most cache.  We assume
  * that this line-size is the same for all CPUs.
  *
  * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
- *
- * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
  */
-static unsigned long
-pci_cacheline_size (void)
+static void __init set_pci_cacheline_size(void)
 {
        u64 levels, unique_caches;
        s64 status;
        pal_cache_config_info_t cci;
-       static u8 cacheline_size;
-
-       if (cacheline_size)
-               return cacheline_size;
 
        status = ia64_pal_cache_summary(&levels, &unique_caches);
        if (status != 0) {
-               printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
-                      __FUNCTION__, status);
-               return SMP_CACHE_BYTES;
+               printk(KERN_ERR "%s: ia64_pal_cache_summary() failed "
+                       "(status=%ld)\n", __func__, status);
+               return;
        }
 
-       status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2,
-                                           &cci);
+       status = ia64_pal_cache_config_info(levels - 1,
+                               /* cache_type (data_or_unified)= */ 2, &cci);
        if (status != 0) {
-               printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
-                      __FUNCTION__, status);
-               return SMP_CACHE_BYTES;
+               printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed "
+                       "(status=%ld)\n", __func__, status);
+               return;
        }
-       cacheline_size = 1 << cci.pcci_line_size;
-       return cacheline_size;
+       pci_cache_line_size = (1 << cci.pcci_line_size) / 4;
 }
 
-/**
- * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
- * @dev: the PCI device for which MWI is enabled
- *
- * For ia64, we can get the cacheline sizes from PAL.
- *
- * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
- */
-int
-pcibios_prep_mwi (struct pci_dev *dev)
+static int __init pcibios_init(void)
 {
-       unsigned long desired_linesize, current_linesize;
-       int rc = 0;
-       u8 pci_linesize;
-
-       desired_linesize = pci_cacheline_size();
-
-       pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize);
-       current_linesize = 4 * pci_linesize;
-       if (desired_linesize != current_linesize) {
-               printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
-                      pci_name(dev), current_linesize);
-               if (current_linesize > desired_linesize) {
-                       printk(" expected %lu bytes instead\n", desired_linesize);
-                       rc = -EINVAL;
-               } else {
-                       printk(" correcting to %lu\n", desired_linesize);
-                       pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4);
-               }
-       }
-       return rc;
+       set_pci_cacheline_size();
+       return 0;
 }
 
-int pci_vector_resources(int last, int nr_released)
-{
-       int count = nr_released;
-
-       count += (IA64_LAST_DEVICE_VECTOR - last);
-
-       return count;
-}
+subsys_initcall(pcibios_init);