*/
#include <linux/device.h>
+#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
+#include <linux/mtd/plat-ram.h>
#include <linux/mtd/physmap.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
};
#endif
+#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
+#ifdef CONFIG_MTD_PARTITIONS
+const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
+
+static struct mtd_partition bfin_plat_nand_partitions[] = {
+ {
+ .name = "linux kernel(nand)",
+ .size = 0x400000,
+ .offset = 0,
+ }, {
+ .name = "file system(nand)",
+ .size = MTDPART_SIZ_FULL,
+ .offset = MTDPART_OFS_APPEND,
+ },
+};
+#endif
+
+#define BFIN_NAND_PLAT_CLE 2
+#define BFIN_NAND_PLAT_ALE 1
+static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+
+ if (cmd == NAND_CMD_NONE)
+ return;
+
+ if (ctrl & NAND_CLE)
+ writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
+ else
+ writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
+}
+
+#define BFIN_NAND_PLAT_READY GPIO_PF3
+static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
+{
+ return gpio_get_value(BFIN_NAND_PLAT_READY);
+}
+
+static struct platform_nand_data bfin_plat_nand_data = {
+ .chip = {
+ .chip_delay = 30,
+#ifdef CONFIG_MTD_PARTITIONS
+ .part_probe_types = part_probes,
+ .partitions = bfin_plat_nand_partitions,
+ .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
+#endif
+ },
+ .ctrl = {
+ .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
+ .dev_ready = bfin_plat_nand_dev_ready,
+ },
+};
+
+#define MAX(x, y) (x > y ? x : y)
+static struct resource bfin_plat_nand_resources = {
+ .start = 0x20212000,
+ .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
+ .flags = IORESOURCE_IO,
+};
+
+static struct platform_device bfin_async_nand_device = {
+ .name = "gen_nand",
+ .id = -1,
+ .num_resources = 1,
+ .resource = &bfin_plat_nand_resources,
+ .dev = {
+ .platform_data = &bfin_plat_nand_data,
+ },
+};
+
+static void bfin_plat_nand_init(void)
+{
+ gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
+}
+#else
+static void bfin_plat_nand_init(void) {}
+#endif
+
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
static struct mtd_partition stamp_partitions[] = {
{
- .name = "Bootloader",
+ .name = "bootloader(nor)",
.size = 0x40000,
.offset = 0,
}, {
- .name = "Kernel",
+ .name = "linux kernel(nor)",
.size = 0xE0000,
.offset = MTDPART_OFS_APPEND,
}, {
- .name = "RootFS",
+ .name = "file system(nor)",
.size = 0x400000 - 0x40000 - 0xE0000 - 0x10000,
.offset = MTDPART_OFS_APPEND,
}, {
- .name = "MAC Address",
+ .name = "MAC Address(nor)",
.size = MTDPART_SIZ_FULL,
.offset = 0x3F0000,
.mask_flags = MTD_WRITEABLE,
};
#endif
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
-/* all SPI peripherals info goes here */
-
#if defined(CONFIG_MTD_M25P80) \
|| defined(CONFIG_MTD_M25P80_MODULE)
static struct mtd_partition bfin_spi_flash_partitions[] = {
{
- .name = "bootloader",
+ .name = "bootloader(spi)",
.size = 0x00040000,
.offset = 0,
.mask_flags = MTD_CAP_ROM
}, {
- .name = "kernel",
+ .name = "linux kernel(spi)",
.size = 0xe0000,
.offset = MTDPART_OFS_APPEND,
}, {
- .name = "file system",
+ .name = "file system(spi)",
.size = MTDPART_SIZ_FULL,
.offset = MTDPART_OFS_APPEND,
}
#if defined(CONFIG_MTD_DATAFLASH) \
|| defined(CONFIG_MTD_DATAFLASH_MODULE)
+
+static struct mtd_partition bfin_spi_dataflash_partitions[] = {
+ {
+ .name = "bootloader(spi)",
+ .size = 0x00040000,
+ .offset = 0,
+ .mask_flags = MTD_CAP_ROM
+ }, {
+ .name = "linux kernel(spi)",
+ .size = 0xe0000,
+ .offset = MTDPART_OFS_APPEND,
+ }, {
+ .name = "file system(spi)",
+ .size = MTDPART_SIZ_FULL,
+ .offset = MTDPART_OFS_APPEND,
+ }
+};
+
+static struct flash_platform_data bfin_spi_dataflash_data = {
+ .name = "SPI Dataflash",
+ .parts = bfin_spi_dataflash_partitions,
+ .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
+};
+
/* DataFlash chip */
static struct bfin5xx_spi_chip data_flash_chip_info = {
.enable_dma = 0, /* use dma transfer with this chip*/
|| defined(CONFIG_MTD_DATAFLASH_MODULE)
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
+ .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0, /* Framework bus number */
.chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
+ .platform_data = &bfin_spi_dataflash_data,
.controller_data = &data_flash_chip_info,
.mode = SPI_MODE_3,
},
#endif
};
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
/* SPI controller data */
static struct bfin5xx_spi_master bfin_spi0_info = {
.num_chipselect = 8,
#endif
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
-#define PATA_INT 55
+#define PATA_INT IRQ_PF5
static struct pata_platform_info bfin_pata_platform_data = {
.ioport_shift = 1,
&bfin_gpios_device,
+#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
+ &bfin_async_nand_device,
+#endif
+
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
&stamp_flash_device,
#endif
ARRAY_SIZE(bfin_i2c_board_info));
#endif
+ bfin_plat_nand_init();
platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
-#endif
+ spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff