Blackfin arch: merge adeos blackfin part to arch/blackfin/

[safe/jmp/linux-2.6] / arch / blackfin / mach-bf527 / include / mach / cdefBF52x_base.h

diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
index 8a374c3..1fe76d8 100644 (file)
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
@@ -1163,7 +1163,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
        if (val == bfin_read_PLL_CTL())
                return;
 
-       local_irq_save(flags);
+       local_irq_save_hw(flags);
        /* Enable the PLL Wakeup bit in SIC IWR */
        iwr0 = bfin_read32(SIC_IWR0);
        iwr1 = bfin_read32(SIC_IWR1);
@@ -1177,7 +1177,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
 
        bfin_write32(SIC_IWR0, iwr0);
        bfin_write32(SIC_IWR1, iwr1);
-       local_irq_restore(flags);
+       local_irq_restore_hw(flags);
 }
 
 /* Writing to VR_CTL initiates a PLL relock sequence. */
@@ -1188,7 +1188,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
        if (val == bfin_read_VR_CTL())
                return;
 
-       local_irq_save(flags);
+       local_irq_save_hw(flags);
        /* Enable the PLL Wakeup bit in SIC IWR */
        iwr0 = bfin_read32(SIC_IWR0);
        iwr1 = bfin_read32(SIC_IWR1);
@@ -1202,7 +1202,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 
        bfin_write32(SIC_IWR0, iwr0);
        bfin_write32(SIC_IWR1, iwr1);
-       local_irq_restore(flags);
+       local_irq_restore_hw(flags);
 }
 
 #endif /* _CDEF_BF52X_H */