Blackfin arch: do not muck with the UART during boot -- let the serial driver worry...

[safe/jmp/linux-2.6] / arch / blackfin / mach-bf527 / head.S

diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S
index af20183..c3334cc 100644 (file)
--- a/arch/blackfin/mach-bf527/head.S
+++ b/arch/blackfin/mach-bf527/head.S
@@ -35,51 +35,6 @@
 #include <asm/mach/mem_init.h>
 #endif
 
-.extern _bf53x_relocate_l1_mem
-
-__INIT
-
-ENTRY(_mach_early_start)
-#if defined(CONFIG_BF527)
-       p0.h = hi(EMAC_SYSTAT);
-       p0.l = lo(EMAC_SYSTAT);
-       R0.h = 0xFFFF; /* Clear EMAC Interrupt Status bits */
-       R0.l = 0xFFFF;
-       [P0] = R0;
-       SSYNC;
-#endif
-
-       /* Initialise UART - when booting from u-boot, the UART is not disabled
-        * so if we dont initalize here, our serial console gets hosed */
-       p0.h = hi(UART1_LCR);
-       p0.l = lo(UART1_LCR);
-       r0 = 0x0(Z);
-       w[p0] = r0.L;   /* To enable DLL writes */
-       ssync;
-
-       p0.h = hi(UART1_DLL);
-       p0.l = lo(UART1_DLL);
-       r0 = 0x0(Z);
-       w[p0] = r0.L;
-       ssync;
-
-       p0.h = hi(UART1_DLH);
-       p0.l = lo(UART1_DLH);
-       r0 = 0x00(Z);
-       w[p0] = r0.L;
-       ssync;
-
-       p0.h = hi(UART1_GCTL);
-       p0.l = lo(UART1_GCTL);
-       r0 = 0x0(Z);
-       w[p0] = r0.L;   /* To enable UART clock */
-       ssync;
-
-       rts;
-ENDPROC(_mach_early_start)
-
-__FINIT
-
 .section .l1.text
 #ifdef CONFIG_BFIN_KERNEL_CLOCK
 ENTRY(_start_dma_code)
@@ -183,13 +138,6 @@ ENTRY(_start_dma_code)
        [P2] = R1;
        SSYNC;
 
-       p0.h = hi(SIC_IWR0);
-       p0.l = lo(SIC_IWR0);
-       r0.l = lo(IWR_ENABLE_ALL);
-       r0.h = hi(IWR_ENABLE_ALL);
-       [p0] = r0;
-       SSYNC;
-
        RTS;
 ENDPROC(_start_dma_code)
 #endif /* CONFIG_BFIN_KERNEL_CLOCK */