/*
* bfin_dma_5xx.c - Blackfin DMA implementation
*
- * Copyright 2004-2006 Analog Devices Inc.
+ * Copyright 2004-2008 Analog Devices Inc.
+ *
* Licensed under the GPL-2 or later.
*/
#include <asm/cacheflush.h>
#include <asm/dma.h>
#include <asm/uaccess.h>
+#include <asm/early_printk.h>
-/**************************************************************************
- * Global Variables
-***************************************************************************/
-
-static struct dma_channel dma_ch[MAX_DMA_CHANNELS];
+/*
+ * To make sure we work around 05000119 - we always check DMA_DONE bit,
+ * never the DMA_RUN bit
+ */
-/*------------------------------------------------------------------------------
- * Set the Buffer Clear bit in the Configuration register of specific DMA
- * channel. This will stop the descriptor based DMA operation.
- *-----------------------------------------------------------------------------*/
-static void clear_dma_buffer(unsigned int channel)
-{
- dma_ch[channel].regs->cfg |= RESTART;
- SSYNC();
- dma_ch[channel].regs->cfg &= ~RESTART;
-}
+struct dma_channel dma_ch[MAX_DMA_CHANNELS];
+EXPORT_SYMBOL(dma_ch);
static int __init blackfin_dma_init(void)
{
printk(KERN_INFO "Blackfin DMA Controller\n");
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
- dma_ch[i].chan_status = DMA_CHANNEL_FREE;
+ atomic_set(&dma_ch[i].chan_status, 0);
dma_ch[i].regs = dma_io_base_addr[i];
- mutex_init(&(dma_ch[i].dmalock));
}
/* Mark MEMDMA Channel 0 as requested since we're using it internally */
request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
int i;
for (i = 0; i < MAX_DMA_CHANNELS; ++i)
- if (dma_ch[i].chan_status != DMA_CHANNEL_FREE)
+ if (dma_channel_active(i))
seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id);
return 0;
late_initcall(proc_dma_init);
#endif
-/*------------------------------------------------------------------------------
- * Request the specific DMA channel from the system.
- *-----------------------------------------------------------------------------*/
+/**
+ * request_dma - request a DMA channel
+ *
+ * Request the specific DMA channel from the system if it's available.
+ */
int request_dma(unsigned int channel, const char *device_id)
{
- pr_debug("request_dma() : BEGIN \n");
+ pr_debug("request_dma() : BEGIN\n");
if (device_id == NULL)
printk(KERN_WARNING "request_dma(%u): no device_id given\n", channel);
}
#endif
- mutex_lock(&(dma_ch[channel].dmalock));
-
- if ((dma_ch[channel].chan_status == DMA_CHANNEL_REQUESTED)
- || (dma_ch[channel].chan_status == DMA_CHANNEL_ENABLED)) {
- mutex_unlock(&(dma_ch[channel].dmalock));
- pr_debug("DMA CHANNEL IN USE \n");
+ if (atomic_cmpxchg(&dma_ch[channel].chan_status, 0, 1)) {
+ pr_debug("DMA CHANNEL IN USE\n");
return -EBUSY;
- } else {
- dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
- pr_debug("DMA CHANNEL IS ALLOCATED \n");
}
- mutex_unlock(&(dma_ch[channel].dmalock));
-
#ifdef CONFIG_BF54x
if (channel >= CH_UART2_RX && channel <= CH_UART3_TX) {
unsigned int per_map;
#endif
dma_ch[channel].device_id = device_id;
- dma_ch[channel].irq_callback = NULL;
+ dma_ch[channel].irq = 0;
/* This is to be enabled by putting a restriction -
* you have to request DMA, before doing any operations on
* descriptor/channel
*/
- pr_debug("request_dma() : END \n");
- return channel;
+ pr_debug("request_dma() : END\n");
+ return 0;
}
EXPORT_SYMBOL(request_dma);
-int set_dma_callback(unsigned int channel, dma_interrupt_t callback, void *data)
+int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data)
{
- BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
- && channel < MAX_DMA_CHANNELS));
-
- if (callback != NULL) {
- int ret_val;
- dma_ch[channel].irq = channel2irq(channel);
- dma_ch[channel].data = data;
-
- ret_val =
- request_irq(dma_ch[channel].irq, callback, IRQF_DISABLED,
- dma_ch[channel].device_id, data);
- if (ret_val) {
- printk(KERN_NOTICE
- "Request irq in DMA engine failed.\n");
- return -EPERM;
- }
- dma_ch[channel].irq_callback = callback;
- }
+ int ret;
+ unsigned int irq;
+
+ BUG_ON(channel >= MAX_DMA_CHANNELS || !callback ||
+ !atomic_read(&dma_ch[channel].chan_status));
+
+ irq = channel2irq(channel);
+ ret = request_irq(irq, callback, 0, dma_ch[channel].device_id, data);
+ if (ret)
+ return ret;
+
+ dma_ch[channel].irq = irq;
+ dma_ch[channel].data = data;
+
return 0;
}
EXPORT_SYMBOL(set_dma_callback);
+/**
+ * clear_dma_buffer - clear DMA fifos for specified channel
+ *
+ * Set the Buffer Clear bit in the Configuration register of specific DMA
+ * channel. This will stop the descriptor based DMA operation.
+ */
+static void clear_dma_buffer(unsigned int channel)
+{
+ dma_ch[channel].regs->cfg |= RESTART;
+ SSYNC();
+ dma_ch[channel].regs->cfg &= ~RESTART;
+}
+
void free_dma(unsigned int channel)
{
- pr_debug("freedma() : BEGIN \n");
- BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
- && channel < MAX_DMA_CHANNELS));
+ pr_debug("freedma() : BEGIN\n");
+ BUG_ON(channel >= MAX_DMA_CHANNELS ||
+ !atomic_read(&dma_ch[channel].chan_status));
/* Halt the DMA */
disable_dma(channel);
clear_dma_buffer(channel);
- if (dma_ch[channel].irq_callback != NULL)
+ if (dma_ch[channel].irq)
free_irq(dma_ch[channel].irq, dma_ch[channel].data);
/* Clear the DMA Variable in the Channel */
- mutex_lock(&(dma_ch[channel].dmalock));
- dma_ch[channel].chan_status = DMA_CHANNEL_FREE;
- mutex_unlock(&(dma_ch[channel].dmalock));
+ atomic_set(&dma_ch[channel].chan_status, 0);
- pr_debug("freedma() : END \n");
+ pr_debug("freedma() : END\n");
}
EXPORT_SYMBOL(free_dma);
-void dma_enable_irq(unsigned int channel)
-{
- pr_debug("dma_enable_irq() : BEGIN \n");
- enable_irq(dma_ch[channel].irq);
-}
-EXPORT_SYMBOL(dma_enable_irq);
-
-void dma_disable_irq(unsigned int channel)
-{
- pr_debug("dma_disable_irq() : BEGIN \n");
- disable_irq(dma_ch[channel].irq);
-}
-EXPORT_SYMBOL(dma_disable_irq);
-
-int dma_channel_active(unsigned int channel)
-{
- if (dma_ch[channel].chan_status == DMA_CHANNEL_FREE) {
- return 0;
- } else {
- return 1;
- }
-}
-EXPORT_SYMBOL(dma_channel_active);
-
-/*------------------------------------------------------------------------------
-* stop the specific DMA channel.
-*-----------------------------------------------------------------------------*/
-void disable_dma(unsigned int channel)
-{
- pr_debug("stop_dma() : BEGIN \n");
- dma_ch[channel].regs->cfg &= ~DMAEN; /* Clean the enable bit */
- SSYNC();
- dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
- /* Needs to be enabled Later */
- pr_debug("stop_dma() : END \n");
- return;
-}
-EXPORT_SYMBOL(disable_dma);
-
-void enable_dma(unsigned int channel)
-{
- pr_debug("enable_dma() : BEGIN \n");
- dma_ch[channel].chan_status = DMA_CHANNEL_ENABLED;
- dma_ch[channel].regs->curr_x_count = 0;
- dma_ch[channel].regs->curr_y_count = 0;
-
- dma_ch[channel].regs->cfg |= DMAEN; /* Set the enable bit */
- pr_debug("enable_dma() : END \n");
- return;
-}
-EXPORT_SYMBOL(enable_dma);
-
-/*------------------------------------------------------------------------------
-* Set the Start Address register for the specific DMA channel
-* This function can be used for register based DMA,
-* to setup the start address
-* addr: Starting address of the DMA Data to be transferred.
-*-----------------------------------------------------------------------------*/
-void set_dma_start_addr(unsigned int channel, unsigned long addr)
-{
- pr_debug("set_dma_start_addr() : BEGIN \n");
- dma_ch[channel].regs->start_addr = addr;
- pr_debug("set_dma_start_addr() : END\n");
-}
-EXPORT_SYMBOL(set_dma_start_addr);
-
-void set_dma_next_desc_addr(unsigned int channel, unsigned long addr)
-{
- pr_debug("set_dma_next_desc_addr() : BEGIN \n");
- dma_ch[channel].regs->next_desc_ptr = addr;
- pr_debug("set_dma_next_desc_addr() : END\n");
-}
-EXPORT_SYMBOL(set_dma_next_desc_addr);
-
-void set_dma_curr_desc_addr(unsigned int channel, unsigned long addr)
-{
- pr_debug("set_dma_curr_desc_addr() : BEGIN \n");
- dma_ch[channel].regs->curr_desc_ptr = addr;
- pr_debug("set_dma_curr_desc_addr() : END\n");
-}
-EXPORT_SYMBOL(set_dma_curr_desc_addr);
-
-void set_dma_x_count(unsigned int channel, unsigned short x_count)
-{
- dma_ch[channel].regs->x_count = x_count;
-}
-EXPORT_SYMBOL(set_dma_x_count);
-
-void set_dma_y_count(unsigned int channel, unsigned short y_count)
-{
- dma_ch[channel].regs->y_count = y_count;
-}
-EXPORT_SYMBOL(set_dma_y_count);
-
-void set_dma_x_modify(unsigned int channel, short x_modify)
-{
- dma_ch[channel].regs->x_modify = x_modify;
-}
-EXPORT_SYMBOL(set_dma_x_modify);
-
-void set_dma_y_modify(unsigned int channel, short y_modify)
-{
- dma_ch[channel].regs->y_modify = y_modify;
-}
-EXPORT_SYMBOL(set_dma_y_modify);
-
-void set_dma_config(unsigned int channel, unsigned short config)
-{
- dma_ch[channel].regs->cfg = config;
-}
-EXPORT_SYMBOL(set_dma_config);
-
-unsigned short
-set_bfin_dma_config(char direction, char flow_mode,
- char intr_mode, char dma_mode, char width, char syncmode)
-{
- unsigned short config;
-
- config =
- ((direction << 1) | (width << 2) | (dma_mode << 4) |
- (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5));
- return config;
-}
-EXPORT_SYMBOL(set_bfin_dma_config);
-
-void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg)
-{
- dma_ch[channel].regs->cfg |= ((nr_sg & 0x0F) << 8);
- dma_ch[channel].regs->next_desc_ptr = (unsigned int)sg;
-}
-EXPORT_SYMBOL(set_dma_sg);
-
-void set_dma_curr_addr(unsigned int channel, unsigned long addr)
-{
- dma_ch[channel].regs->curr_addr_ptr = addr;
-}
-EXPORT_SYMBOL(set_dma_curr_addr);
-
-/*------------------------------------------------------------------------------
- * Get the DMA status of a specific DMA channel from the system.
- *-----------------------------------------------------------------------------*/
-unsigned short get_dma_curr_irqstat(unsigned int channel)
-{
- return dma_ch[channel].regs->irq_status;
-}
-EXPORT_SYMBOL(get_dma_curr_irqstat);
-
-/*------------------------------------------------------------------------------
- * Clear the DMA_DONE bit in DMA status. Stop the DMA completion interrupt.
- *-----------------------------------------------------------------------------*/
-void clear_dma_irqstat(unsigned int channel)
-{
- dma_ch[channel].regs->irq_status |= 3;
-}
-EXPORT_SYMBOL(clear_dma_irqstat);
-
-/*------------------------------------------------------------------------------
- * Get current DMA xcount of a specific DMA channel from the system.
- *-----------------------------------------------------------------------------*/
-unsigned short get_dma_curr_xcount(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_x_count;
-}
-EXPORT_SYMBOL(get_dma_curr_xcount);
-
-/*------------------------------------------------------------------------------
- * Get current DMA ycount of a specific DMA channel from the system.
- *-----------------------------------------------------------------------------*/
-unsigned short get_dma_curr_ycount(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_y_count;
-}
-EXPORT_SYMBOL(get_dma_curr_ycount);
-
-unsigned long get_dma_next_desc_ptr(unsigned int channel)
-{
- return dma_ch[channel].regs->next_desc_ptr;
-}
-EXPORT_SYMBOL(get_dma_next_desc_ptr);
-
-unsigned long get_dma_curr_desc_ptr(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_desc_ptr;
-}
-EXPORT_SYMBOL(get_dma_curr_desc_ptr);
-
-unsigned long get_dma_curr_addr(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_addr_ptr;
-}
-EXPORT_SYMBOL(get_dma_curr_addr);
-
#ifdef CONFIG_PM
# ifndef MAX_DMA_SUSPEND_CHANNELS
# define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS
{
int i;
- for (i = 0; i < MAX_DMA_SUSPEND_CHANNELS; ++i) {
- if (dma_ch[i].chan_status == DMA_CHANNEL_ENABLED) {
+ for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
+ if (dma_ch[i].regs->cfg & DMAEN) {
printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
return -EBUSY;
}
- dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
+ if (i < MAX_DMA_SUSPEND_CHANNELS)
+ dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
}
return 0;
void blackfin_dma_resume(void)
{
int i;
- for (i = 0; i < MAX_DMA_SUSPEND_CHANNELS; ++i)
- dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
+
+ for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
+ dma_ch[i].regs->cfg = 0;
+
+ if (i < MAX_DMA_SUSPEND_CHANNELS)
+ dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
+ }
}
#endif
*/
void __init blackfin_dma_early_init(void)
{
+ early_shadow_stamp();
bfin_write_MDMA_S0_CONFIG(0);
+ bfin_write_MDMA_S1_CONFIG(0);
+}
+
+void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
+{
+ unsigned long dst = (unsigned long)pdst;
+ unsigned long src = (unsigned long)psrc;
+ struct dma_register *dst_ch, *src_ch;
+
+ early_shadow_stamp();
+
+ /* We assume that everything is 4 byte aligned, so include
+ * a basic sanity check
+ */
+ BUG_ON(dst % 4);
+ BUG_ON(src % 4);
+ BUG_ON(size % 4);
+
+ src_ch = 0;
+ /* Find an avalible memDMA channel */
+ while (1) {
+ if (src_ch == (struct dma_register *)MDMA_S0_NEXT_DESC_PTR) {
+ dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR;
+ src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR;
+ } else {
+ dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR;
+ src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
+ }
+
+ if (!bfin_read16(&src_ch->cfg))
+ break;
+ else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) {
+ bfin_write16(&src_ch->cfg, 0);
+ break;
+ }
+ }
+
+ /* Force a sync in case a previous config reset on this channel
+ * occurred. This is needed so subsequent writes to DMA registers
+ * are not spuriously lost/corrupted.
+ */
+ __builtin_bfin_ssync();
+
+ /* Destination */
+ bfin_write32(&dst_ch->start_addr, dst);
+ bfin_write16(&dst_ch->x_count, size >> 2);
+ bfin_write16(&dst_ch->x_modify, 1 << 2);
+ bfin_write16(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
+
+ /* Source */
+ bfin_write32(&src_ch->start_addr, src);
+ bfin_write16(&src_ch->x_count, size >> 2);
+ bfin_write16(&src_ch->x_modify, 1 << 2);
+ bfin_write16(&src_ch->irq_status, DMA_DONE | DMA_ERR);
+
+ /* Enable */
+ bfin_write16(&src_ch->cfg, DMAEN | WDSIZE_32);
+ bfin_write16(&dst_ch->cfg, WNR | DI_EN | DMAEN | WDSIZE_32);
+
+ /* Since we are atomic now, don't use the workaround ssync */
+ __builtin_bfin_ssync();
+}
+
+void __init early_dma_memcpy_done(void)
+{
+ early_shadow_stamp();
+
+ while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) ||
+ (bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE)))
+ continue;
+
+ bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+ bfin_write_MDMA_D1_IRQ_STATUS(DMA_DONE | DMA_ERR);
+ /*
+ * Now that DMA is done, we would normally flush cache, but
+ * i/d cache isn't running this early, so we don't bother,
+ * and just clear out the DMA channel for next time
+ */
+ bfin_write_MDMA_S0_CONFIG(0);
+ bfin_write_MDMA_S1_CONFIG(0);
+ bfin_write_MDMA_D0_CONFIG(0);
+ bfin_write_MDMA_D1_CONFIG(0);
+
+ __builtin_bfin_ssync();
}
/**
spin_lock_irqsave(&mdma_lock, flags);
+ /* Force a sync in case a previous config reset on this channel
+ * occurred. This is needed so subsequent writes to DMA registers
+ * are not spuriously lost/corrupted. Do it under irq lock and
+ * without the anomaly version (because we are atomic already).
+ */
+ __builtin_bfin_ssync();
+
if (bfin_read_MDMA_S0_CONFIG())
while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
continue;
* _dma_memcpy - translate C memcpy settings into MDMA settings
*
* Handle all the high level steps before we touch the MDMA registers. So
- * handle caching, tweaking of sizes, and formatting of addresses.
+ * handle direction, tweaking of sizes, and formatting of addresses.
*/
static void *_dma_memcpy(void *pdst, const void *psrc, size_t size)
{
if (size == 0)
return NULL;
- if (bfin_addr_dcachable(src))
- blackfin_dcache_flush_range(src, src + size);
-
- if (bfin_addr_dcachable(dst))
- blackfin_dcache_invalidate_range(dst, dst + size);
-
if (dst % 4 == 0 && src % 4 == 0 && size % 4 == 0) {
conf = WDSIZE_32;
shift = 2;
* up into two pieces. The first transfer is in multiples of 64k and the
* second transfer is the piece smaller than 64k.
*/
-void *dma_memcpy(void *dst, const void *src, size_t size)
+void *dma_memcpy(void *pdst, const void *psrc, size_t size)
{
+ unsigned long dst = (unsigned long)pdst;
+ unsigned long src = (unsigned long)psrc;
size_t bulk, rest;
+
+ if (bfin_addr_dcacheable(src))
+ blackfin_dcache_flush_range(src, src + size);
+
+ if (bfin_addr_dcacheable(dst))
+ blackfin_dcache_invalidate_range(dst, dst + size);
+
bulk = size & ~0xffff;
rest = size - bulk;
if (bulk)
- _dma_memcpy(dst, src, bulk);
- _dma_memcpy(dst + bulk, src + bulk, rest);
- return dst;
+ _dma_memcpy(pdst, psrc, bulk);
+ _dma_memcpy(pdst + bulk, psrc + bulk, rest);
+ return pdst;
}
EXPORT_SYMBOL(dma_memcpy);
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff