config BF561
bool "BF561"
help
- Not Supported Yet - Work in progress - BF561 Processor Support.
+ BF561 Processor Support.
endchoice
+config BF_REV_MIN
+ int
+ default 0 if (BF52x || BF54x)
+ default 2 if (BF537 || BF536 || BF534)
+ default 3 if (BF561 ||BF533 || BF532 || BF531)
+
+config BF_REV_MAX
+ int
+ default 2 if (BF52x || BF54x)
+ default 3 if (BF537 || BF536 || BF534)
+ default 5 if (BF561)
+ default 6 if (BF533 || BF532 || BF531)
+
choice
prompt "Silicon Rev"
- default BF_REV_0_1 if BF527
- default BF_REV_0_2 if BF537
- default BF_REV_0_3 if BF533
- default BF_REV_0_0 if BF549
+ default BF_REV_0_1 if (BF52x || BF54x)
+ default BF_REV_0_2 if (BF534 || BF536 || BF537)
+ default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
config BF_REV_0_0
bool "0.0"
config BF_REV_0_2
bool "0.2"
- depends on (BF537 || BF536 || BF534)
+ depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
config BF_REV_0_3
bool "0.3"
bool "0.5"
depends on (BF561 || BF533 || BF532 || BF531)
+config BF_REV_0_6
+ bool "0.6"
+ depends on (BF533 || BF532 || BF531)
+
config BF_REV_ANY
bool "any"
bool
depends on (BFIN533_EZKIT || BFIN561_EZKIT \
|| BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
- || H8606_HVSISTEMAS)
+ || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
default y
config MEM_MT48LC32M8A2_75
config MEM_MT48LC32M16A2TG_75
bool
- depends on (BFIN527_EZKIT || BFIN532_IP0X)
+ depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
default y
source "arch/blackfin/mach-bf527/Kconfig"
memory region is used to capture NULL pointer references as well
as some core kernel functions.
+config ROM_BASE
+ hex "Kernel ROM Base"
+ default "0x20040000"
+ range 0x20000000 0x20400000 if !(BF54x || BF561)
+ range 0x20000000 0x30000000 if (BF54x || BF561)
+ help
+
comment "Clock/PLL Setup"
config CLKIN_HZ
int "Frequency of the crystal on the board in Hz"
default "11059200" if BFIN533_STAMP
default "27000000" if BFIN533_EZKIT
- default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
+ default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
default "30000000" if BFIN561_EZKIT
default "24576000" if PNAV10
default "10000000" if BFIN532_IP0X
default "45" if BFIN533_STAMP
default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
default "22" if BFIN533_BLUETECHNIX_CM
- default "20" if BFIN537_BLUETECHNIX_CM
- default "20" if BFIN561_BLUETECHNIX_CM
+ default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
default "20" if BFIN561_EZKIT
- default "16" if H8606_HVSISTEMAS
+ default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
help
This controls the frequency of the on-chip PLL. This can be between 1 and 64.
PLL Frequency = (Crystal Frequency) * (this setting)
This can be between 1 and 15
System Clock = (PLL frequency) / (this setting)
-config MAX_MEM_SIZE
- int "Max SDRAM Memory Size in MBytes"
- depends on !MPU
- default 512
- help
- This is the max memory size that the kernel will create CPLB
- tables for. Your system will not be able to handle any more.
-
choice
prompt "DDR SDRAM Chip Type"
depends on BFIN_KERNEL_CLOCK
bool "MT46V32M16_5B"
endchoice
+config MAX_MEM_SIZE
+ int "Max SDRAM Memory Size in MBytes"
+ depends on !MPU
+ default 512
+ help
+ This is the max memory size that the kernel will create CPLB
+ tables for. Your system will not be able to handle any more.
+
#
# Max & Min Speeds for various Chips
#
source kernel/time/Kconfig
-comment "Memory Setup"
-
comment "Misc"
choice
If enabled, the CPLB Switch Tables are linked
into L1 data memory. (less latency)
+config APP_STACK_L1
+ bool "Support locating application stack in L1 Scratch Memory"
+ default y
+ help
+ If enabled the application stack can be located in L1
+ scratch memory (less latency).
+
+ Currently only works with FLAT binaries.
+
+comment "Speed Optimizations"
+config BFIN_INS_LOWOVERHEAD
+ bool "ins[bwl] low overhead, higher interrupt latency"
+ default y
+ help
+ Reads on the Blackfin are speculative. In Blackfin terms, this means
+ they can be interrupted at any time (even after they have been issued
+ on to the external bus), and re-issued after the interrupt occurs.
+ For memory - this is not a big deal, since memory does not change if
+ it sees a read.
+
+ If a FIFO is sitting on the end of the read, it will see two reads,
+ when the core only sees one since the FIFO receives both the read
+ which is cancelled (and not delivered to the core) and the one which
+ is re-issued (which is delivered to the core).
+
+ To solve this, interrupts are turned off before reads occur to
+ I/O space. This option controls which the overhead/latency of
+ controlling interrupts during this time
+ "n" turns interrupts off every read
+ (higher overhead, but lower interrupt latency)
+ "y" turns interrupts off every loop
+ (low overhead, but longer interrupt latency)
+
+ default behavior is to leave this set to on (type "Y"). If you are experiencing
+ interrupt latency issues, it is safe and OK to turn this off.
+
endmenu
endchoice
+config BFIN_L2_CACHEABLE
+ bool "Cache L2 SRAM"
+ depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
+ default n
+ help
+ Select to make L2 SRAM cacheable in L1 data and instruction cache.
+
config MPU
bool "Enable the memory protection unit (EXPERIMENTAL)"
default n
config PCI
bool "PCI support"
+ depends on BROKEN
help
Support for PCI bus.
plugged into slots found on all modern laptop computers. Another
example, used on modern desktops as well as laptops, is USB.
- Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
- software (at <http://linux-hotplug.sourceforge.net/>) and install it.
+ Enable HOTPLUG and build a modular kernel. Get agent software
+ (from <http://linux-hotplug.sourceforge.net/>) and install it.
Then your kernel will automatically call out to a user mode "policy
agent" (/sbin/hotplug) to load modules and set up software needed
to use devices as you hotplug them.
comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
depends on PM
-config PM_BFIN_WAKE_RTC
- bool "Allow Wake-Up from RESET and on-chip RTC"
- depends on PM
- default n
- help
- Enable RTC Wake-Up (Voltage Regulator Power-Up)
-
config PM_BFIN_WAKE_PH6
bool "Allow Wake-Up from on-chip PHY or PH6 GP"
depends on PM && (BF52x || BF534 || BF536 || BF537)
help
Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
-config PM_BFIN_WAKE_CAN
- bool "Allow Wake-Up from on-chip CAN0/1"
- depends on PM && (BF54x || BF534 || BF536 || BF537)
- default n
- help
- Enable CAN0/1 Wake-Up (Voltage Regulator Power-Up)
-
config PM_BFIN_WAKE_GP
bool "Allow Wake-Up from GPIOs"
depends on PM && BF54x
default n
help
Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
-
-config PM_BFIN_WAKE_USB
- bool "Allow Wake-Up from on-chip USB"
- depends on PM && (BF54x || BF52x)
- default n
- help
- Enable USB Wake-Up (Voltage Regulator Power-Up)
-
-config PM_BFIN_WAKE_KEYPAD
- bool "Allow Wake-Up from on-chip Keypad"
- depends on PM && BF54x
- default n
- help
- Enable Keypad Wake-Up (Voltage Regulator Power-Up)
-
-config PM_BFIN_WAKE_ROTARY
- bool "Allow Wake-Up from on-chip Rotary"
- depends on PM && BF54x
- default n
- help
- Enable Rotary Wake-Up (Voltage Regulator Power-Up)
-
endmenu
menu "CPU Frequency scaling"
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff