config BLACKFIN
bool
default y
+ select HAVE_IDE
+ select HAVE_OPROFILE
+ select ARCH_WANT_OPTIONAL_GPIOLIB
config ZONE_DMA
bool
default y
-config SEMAPHORE_SLEEPERS
- bool
- default y
-
config GENERIC_FIND_NEXT_BIT
bool
default y
bool
default y
-config GENERIC_TIME
- bool
- default n
-
config GENERIC_GPIO
bool
default y
bool
default y
-config IRQCHIP_DEMUX_GPIO
- bool
- depends on (BF52x || BF53x || BF561 || BF54x)
- default y
-
source "init/Kconfig"
+
source "kernel/Kconfig.preempt"
+source "kernel/Kconfig.freezer"
+
menu "Blackfin Processor Options"
comment "Processor and Board Settings"
prompt "CPU"
default BF533
+config BF512
+ bool "BF512"
+ help
+ BF512 Processor Support.
+
+config BF514
+ bool "BF514"
+ help
+ BF514 Processor Support.
+
+config BF516
+ bool "BF516"
+ help
+ BF516 Processor Support.
+
+config BF518
+ bool "BF518"
+ help
+ BF518 Processor Support.
+
config BF522
bool "BF522"
help
BF522 Processor Support.
+config BF523
+ bool "BF523"
+ help
+ BF523 Processor Support.
+
+config BF524
+ bool "BF524"
+ help
+ BF524 Processor Support.
+
config BF525
bool "BF525"
help
BF525 Processor Support.
+config BF526
+ bool "BF526"
+ help
+ BF526 Processor Support.
+
config BF527
bool "BF527"
help
help
BF537 Processor Support.
+config BF538
+ bool "BF538"
+ help
+ BF538 Processor Support.
+
+config BF539
+ bool "BF539"
+ help
+ BF539 Processor Support.
+
config BF542
bool "BF542"
help
config BF561
bool "BF561"
help
- Not Supported Yet - Work in progress - BF561 Processor Support.
+ BF561 Processor Support.
endchoice
+config SMP
+ depends on BF561
+ bool "Symmetric multi-processing support"
+ ---help---
+ This enables support for systems with more than one CPU,
+ like the dual core BF561. If you have a system with only one
+ CPU, say N. If you have a system with more than one CPU, say Y.
+
+ If you don't know what to do here, say N.
+
+config NR_CPUS
+ int
+ depends on SMP
+ default 2 if BF561
+
+config IRQ_PER_CPU
+ bool
+ depends on SMP
+ default y
+
+config TICK_SOURCE_SYSTMR0
+ bool
+ select BFIN_GPTIMERS
+ depends on SMP
+ default y
+
+config BF_REV_MIN
+ int
+ default 0 if (BF51x || BF52x || BF54x)
+ default 2 if (BF537 || BF536 || BF534)
+ default 3 if (BF561 ||BF533 || BF532 || BF531)
+ default 4 if (BF538 || BF539)
+
+config BF_REV_MAX
+ int
+ default 2 if (BF51x || BF52x || BF54x)
+ default 3 if (BF537 || BF536 || BF534)
+ default 5 if (BF561 || BF538 || BF539)
+ default 6 if (BF533 || BF532 || BF531)
+
choice
prompt "Silicon Rev"
- default BF_REV_0_1 if BF527
- default BF_REV_0_2 if BF537
- default BF_REV_0_3 if BF533
- default BF_REV_0_0 if BF549
+ default BF_REV_0_1 if (BF51x || BF52x || BF54x)
+ default BF_REV_0_2 if (BF534 || BF536 || BF537)
+ default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
config BF_REV_0_0
bool "0.0"
- depends on (BF52x || BF54x)
+ depends on (BF51x || BF52x || BF54x)
config BF_REV_0_1
bool "0.1"
config BF_REV_0_2
bool "0.2"
- depends on (BF537 || BF536 || BF534)
+ depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
config BF_REV_0_3
bool "0.3"
config BF_REV_0_4
bool "0.4"
- depends on (BF561 || BF533 || BF532 || BF531)
+ depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
config BF_REV_0_5
bool "0.5"
- depends on (BF561 || BF533 || BF532 || BF531)
+ depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
+
+config BF_REV_0_6
+ bool "0.6"
+ depends on (BF533 || BF532 || BF531)
config BF_REV_ANY
bool "any"
endchoice
+config BF51x
+ bool
+ depends on (BF512 || BF514 || BF516 || BF518)
+ default y
+
config BF52x
bool
- depends on (BF522 || BF525 || BF527)
+ depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
default y
config BF53x
depends on (BF542 || BF544 || BF547 || BF548 || BF549)
default y
-config BFIN_DUAL_CORE
- bool
- depends on (BF561)
- default y
-
-config BFIN_SINGLE_CORE
- bool
- depends on !BFIN_DUAL_CORE
- default y
-
config MEM_GENERIC_BOARD
bool
depends on GENERIC_BOARD
bool
depends on (BFIN533_EZKIT || BFIN561_EZKIT \
|| BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
- || H8606_HVSISTEMAS)
+ || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
default y
config MEM_MT48LC32M8A2_75
bool
- depends on (BFIN537_STAMP || PNAV10)
+ depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
default y
config MEM_MT48LC8M32B2B5_7
config MEM_MT48LC32M16A2TG_75
bool
- depends on (BFIN527_EZKIT)
- default y
-
-config BFIN_SHARED_FLASH_ENET
- bool
- depends on (BFIN533_STAMP)
+ depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
default y
+source "arch/blackfin/mach-bf518/Kconfig"
source "arch/blackfin/mach-bf527/Kconfig"
source "arch/blackfin/mach-bf533/Kconfig"
source "arch/blackfin/mach-bf561/Kconfig"
source "arch/blackfin/mach-bf537/Kconfig"
+source "arch/blackfin/mach-bf538/Kconfig"
source "arch/blackfin/mach-bf548/Kconfig"
menu "Board customizations"
to the kernel, you may specify one here. As a minimum, you should specify
the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
+config BOOT_LOAD
+ hex "Kernel load address for booting"
+ default "0x1000"
+ range 0x1000 0x20000000
+ help
+ This option allows you to set the load address of the kernel.
+ This can be useful if you are on a board which has a small amount
+ of memory or you wish to reserve some memory at the beginning of
+ the address space.
+
+ Note that you need to keep this value above 4k (0x1000) as this
+ memory region is used to capture NULL pointer references as well
+ as some core kernel functions.
+
+config ROM_BASE
+ hex "Kernel ROM Base"
+ depends on ROMKERNEL
+ default "0x20040000"
+ range 0x20000000 0x20400000 if !(BF54x || BF561)
+ range 0x20000000 0x30000000 if (BF54x || BF561)
+ help
+
comment "Clock/PLL Setup"
config CLKIN_HZ
- int "Crystal Frequency in Hz"
+ int "Frequency of the crystal on the board in Hz"
default "11059200" if BFIN533_STAMP
default "27000000" if BFIN533_EZKIT
- default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
+ default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
default "30000000" if BFIN561_EZKIT
default "24576000" if PNAV10
+ default "10000000" if BFIN532_IP0X
help
The frequency of CLKIN crystal oscillator on the board in Hz.
+ Warning: This value should match the crystal on the board. Otherwise,
+ peripherals won't work properly.
config BFIN_KERNEL_CLOCK
bool "Re-program Clocks while Kernel boots?"
range 1 64
default "22" if BFIN533_EZKIT
default "45" if BFIN533_STAMP
- default "20" if (BFIN537_STAMP || BFIN527_EZKIT)
+ default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
default "22" if BFIN533_BLUETECHNIX_CM
- default "20" if BFIN537_BLUETECHNIX_CM
- default "20" if BFIN561_BLUETECHNIX_CM
+ default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
default "20" if BFIN561_EZKIT
- default "16" if H8606_HVSISTEMAS
+ default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
help
This controls the frequency of the on-chip PLL. This can be between 1 and 64.
PLL Frequency = (Crystal Frequency) * (this setting)
int "System Clock Divider"
depends on BFIN_KERNEL_CLOCK
range 1 15
- default 5 if BFIN533_EZKIT
- default 5 if BFIN533_STAMP
- default 4 if (BFIN537_STAMP || BFIN527_EZKIT)
- default 5 if BFIN533_BLUETECHNIX_CM
- default 4 if BFIN537_BLUETECHNIX_CM
- default 4 if BFIN561_BLUETECHNIX_CM
- default 5 if BFIN561_EZKIT
- default 3 if H8606_HVSISTEMAS
+ default 5
help
This sets the frequency of the system clock (including SDRAM or DDR).
This can be between 1 and 15
System Clock = (PLL frequency) / (this setting)
+choice
+ prompt "DDR SDRAM Chip Type"
+ depends on BFIN_KERNEL_CLOCK
+ depends on BF54x
+ default MEM_MT46V32M16_5B
+
+config MEM_MT46V32M16_6T
+ bool "MT46V32M16_6T"
+
+config MEM_MT46V32M16_5B
+ bool "MT46V32M16_5B"
+endchoice
+
+choice
+ prompt "DDR/SDRAM Timing"
+ depends on BFIN_KERNEL_CLOCK
+ default BFIN_KERNEL_CLOCK_MEMINIT_CALC
+ help
+ This option allows you to specify Blackfin SDRAM/DDR Timing parameters
+ The calculated SDRAM timing parameters may not be 100%
+ accurate - This option is therefore marked experimental.
+
+config BFIN_KERNEL_CLOCK_MEMINIT_CALC
+ bool "Calculate Timings (EXPERIMENTAL)"
+ depends on EXPERIMENTAL
+
+config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
+ bool "Provide accurate Timings based on target SCLK"
+ help
+ Please consult the Blackfin Hardware Reference Manuals as well
+ as the memory device datasheet.
+ http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
+endchoice
+
+menu "Memory Init Control"
+ depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
+
+config MEM_DDRCTL0
+ depends on BF54x
+ hex "DDRCTL0"
+ default 0x0
+
+config MEM_DDRCTL1
+ depends on BF54x
+ hex "DDRCTL1"
+ default 0x0
+
+config MEM_DDRCTL2
+ depends on BF54x
+ hex "DDRCTL2"
+ default 0x0
+
+config MEM_EBIU_DDRQUE
+ depends on BF54x
+ hex "DDRQUE"
+ default 0x0
+
+config MEM_SDRRC
+ depends on !BF54x
+ hex "SDRRC"
+ default 0x0
+
+config MEM_SDGCTL
+ depends on !BF54x
+ hex "SDGCTL"
+ default 0x0
+endmenu
+
#
# Max & Min Speeds for various Chips
#
config MAX_VCO_HZ
int
+ default 400000000 if BF512
+ default 400000000 if BF514
+ default 400000000 if BF516
+ default 400000000 if BF518
default 600000000 if BF522
+ default 400000000 if BF523
+ default 400000000 if BF524
default 600000000 if BF525
+ default 400000000 if BF526
default 600000000 if BF527
default 400000000 if BF531
default 400000000 if BF532
default 500000000 if BF534
default 400000000 if BF536
default 600000000 if BF537
- default 533000000 if BF538
- default 533000000 if BF539
+ default 533333333 if BF538
+ default 533333333 if BF539
default 600000000 if BF542
- default 533000000 if BF544
- default 533000000 if BF549
+ default 533333333 if BF544
+ default 600000000 if BF547
+ default 600000000 if BF548
+ default 533333333 if BF549
default 600000000 if BF561
config MIN_VCO_HZ
config MAX_SCLK_HZ
int
- default 133000000
+ default 133333333
config MIN_SCLK_HZ
int
source kernel/Kconfig.hz
-comment "Memory Setup"
-
-config MEM_SIZE
- int "SDRAM Memory Size in MBytes"
- default 32 if BFIN533_EZKIT
- default 64 if BFIN527_EZKIT
- default 64 if BFIN537_STAMP
- default 64 if BFIN561_EZKIT
- default 128 if BFIN533_STAMP
- default 64 if PNAV10
- default 32 if H8606_HVSISTEMAS
-
-config MEM_ADD_WIDTH
- int "SDRAM Memory Address Width"
- default 9 if BFIN533_EZKIT
- default 9 if BFIN561_EZKIT
- default 9 if H8606_HVSISTEMAS
- default 10 if BFIN527_EZKIT
- default 10 if BFIN537_STAMP
- default 11 if BFIN533_STAMP
- default 10 if PNAV10
-
-config ENET_FLASH_PIN
- int "PF port/pin used for flash and ethernet sharing"
- depends on (BFIN533_STAMP)
- default 0
- help
- PF port/pin used for flash and ethernet sharing to allow other PF
- pins to be used on other platforms without having to touch common
- code.
- For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc.
-
-config BOOT_LOAD
- hex "Kernel load address for booting"
- default "0x1000"
- range 0x1000 0x20000000
- help
- This option allows you to set the load address of the kernel.
- This can be useful if you are on a board which has a small amount
- of memory or you wish to reserve some memory at the beginning of
- the address space.
-
- Note that you need to keep this value above 4k (0x1000) as this
- memory region is used to capture NULL pointer references as well
- as some core kernel functions.
+config GENERIC_TIME
+ bool "Generic time"
+ depends on !SMP
+ default y
-comment "LED Status Indicators"
- depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
+config GENERIC_CLOCKEVENTS
+ bool "Generic clock events"
+ depends on GENERIC_TIME
+ default y
-config BFIN_ALIVE_LED
- bool "Enable Board Alive"
- depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
+config CYCLES_CLOCKSOURCE
+ bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
+ depends on EXPERIMENTAL
+ depends on GENERIC_CLOCKEVENTS
+ depends on !BFIN_SCRATCH_REG_CYCLES
default n
help
- Blink the LEDs you select when the kernel is running. Helps detect
- a hung kernel.
+ If you say Y here, you will enable support for using the 'cycles'
+ registers as a clock source. Doing so means you will be unable to
+ safely write to the 'cycles' register during runtime. You will
+ still be able to read it (such as for performance monitoring), but
+ writing the registers will most likely crash the kernel.
-config BFIN_ALIVE_LED_NUM
- int "LED"
- depends on BFIN_ALIVE_LED
- range 1 3 if BFIN533_STAMP
- default "3" if BFIN533_STAMP
- help
- Select the LED (marked on the board) for you to blink.
+source kernel/time/Kconfig
-config BFIN_IDLE_LED
- bool "Enable System Load/Idle LED"
- depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
- default n
- help
- Blinks the LED you select when to determine kernel load.
-
-config BFIN_IDLE_LED_NUM
- int "LED"
- depends on BFIN_IDLE_LED
- range 1 3 if BFIN533_STAMP
- default "2" if BFIN533_STAMP
- help
- Select the LED (marked on the board) for you to blink.
+comment "Misc"
choice
prompt "Blackfin Exception Scratch Register"
endchoice
-#
-# Sorry - but you need to put the hex address here -
-#
-
-# Flag Data register
-config BFIN_ALIVE_LED_PORT
- hex
- default 0xFFC00700 if (BFIN533_STAMP)
-
-# Peripheral Flag Direction Register
-config BFIN_ALIVE_LED_DPORT
- hex
- default 0xFFC00730 if (BFIN533_STAMP)
-
-config BFIN_ALIVE_LED_PIN
- hex
- default 0x04 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 1)
- default 0x08 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 2)
- default 0x10 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 3)
-
-config BFIN_IDLE_LED_PORT
- hex
- default 0xFFC00700 if (BFIN533_STAMP)
-
-# Peripheral Flag Direction Register
-config BFIN_IDLE_LED_DPORT
- hex
- default 0xFFC00730 if (BFIN533_STAMP)
-
-config BFIN_IDLE_LED_PIN
- hex
- default 0x04 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 1)
- default 0x08 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 2)
- default 0x10 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 3)
-
endmenu
menu "Blackfin Kernel Optimizations"
+ depends on !SMP
comment "Memory Optimizations"
default y
help
If enabled, the entire ASM lowlevel exception and interrupt entry code
- (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
+ (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
(less latency)
config DO_IRQ_L1
If enabled, the CPLB Switch Tables are linked
into L1 data memory. (less latency)
-endmenu
+config APP_STACK_L1
+ bool "Support locating application stack in L1 Scratch Memory"
+ default y
+ help
+ If enabled the application stack can be located in L1
+ scratch memory (less latency).
+
+ Currently only works with FLAT binaries.
+
+config EXCEPTION_L1_SCRATCH
+ bool "Locate exception stack in L1 Scratch Memory"
+ default n
+ depends on !APP_STACK_L1 && !SYSCALL_TAB_L1
+ help
+ Whenever an exception occurs, use the L1 Scratch memory for
+ stack storage. You cannot place the stacks of FLAT binaries
+ in L1 when using this option.
+ If you don't use L1 Scratch, then you should say Y here.
+
+comment "Speed Optimizations"
+config BFIN_INS_LOWOVERHEAD
+ bool "ins[bwl] low overhead, higher interrupt latency"
+ default y
+ help
+ Reads on the Blackfin are speculative. In Blackfin terms, this means
+ they can be interrupted at any time (even after they have been issued
+ on to the external bus), and re-issued after the interrupt occurs.
+ For memory - this is not a big deal, since memory does not change if
+ it sees a read.
+
+ If a FIFO is sitting on the end of the read, it will see two reads,
+ when the core only sees one since the FIFO receives both the read
+ which is cancelled (and not delivered to the core) and the one which
+ is re-issued (which is delivered to the core).
+
+ To solve this, interrupts are turned off before reads occur to
+ I/O space. This option controls which the overhead/latency of
+ controlling interrupts during this time
+ "n" turns interrupts off every read
+ (higher overhead, but lower interrupt latency)
+ "y" turns interrupts off every loop
+ (low overhead, but longer interrupt latency)
+
+ default behavior is to leave this set to on (type "Y"). If you are experiencing
+ interrupt latency issues, it is safe and OK to turn this off.
+
+endmenu
choice
prompt "Kernel executes from"
source "mm/Kconfig"
-config LARGE_ALLOCS
- bool "Allow allocating large blocks (> 1MB) of memory"
- help
- Allow the slab memory allocator to keep chains for very large
- memory sizes - upto 32MB. You may need this if your system has
- a lot of RAM, and you need to able to allocate very large
- contiguous chunks. If unsure, say N.
-
config BFIN_GPTIMERS
tristate "Enable Blackfin General Purpose Timers API"
default n
To compile this driver as a module, choose M here: the module
will be called gptimers.ko.
-config BFIN_DMA_5XX
- bool "Enable DMA Support"
- depends on (BF52x || BF53x || BF561 || BF54x)
- default y
- help
- DMA driver for BF5xx.
-
choice
- prompt "Uncached SDRAM region"
+ prompt "Uncached DMA region"
default DMA_UNCACHED_1M
- depends on BFIN_DMA_5XX
+config DMA_UNCACHED_4M
+ bool "Enable 4M DMA region"
config DMA_UNCACHED_2M
bool "Enable 2M DMA region"
config DMA_UNCACHED_1M
choice
prompt "Policy"
depends on BFIN_DCACHE
- default BFIN_WB
+ default BFIN_WB if !SMP
+ default BFIN_WT if SMP
config BFIN_WB
bool "Write back"
+ depends on !SMP
help
Write Back Policy:
Cached data will be written back to SDRAM only when needed.
endchoice
-config L1_MAX_PIECE
- int "Set the max L1 SRAM pieces"
- default 16
+config BFIN_L2_CACHEABLE
+ bool "Cache L2 SRAM"
+ depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
+ default n
help
- Set the max memory pieces for the L1 SRAM allocation algorithm.
- Min value is 16. Max value is 1024.
+ Select to make L2 SRAM cacheable in L1 data and instruction cache.
+
+config MPU
+ bool "Enable the memory protection unit (EXPERIMENTAL)"
+ default n
+ help
+ Use the processor's MPU to protect applications from accessing
+ memory they do not own. This comes at a performance penalty
+ and is recommended only for debugging.
comment "Asynchonous Memory Configuration"
config C_CDPRIO
bool "DMA has priority over core for ext. accesses"
- depends on !BF54x
default n
config C_B0PEN
config BANK_1
hex "Bank 1"
default 0x7BB0
+ default 0x5558 if BF54x
config BANK_2
hex "Bank 2"
default 0x99B3
endmenu
+config EBIU_MBSCTLVAL
+ hex "EBIU Bank Select Control Register"
+ depends on BF54x
+ default 0
+
+config EBIU_MODEVAL
+ hex "Flash Memory Mode Control Register"
+ depends on BF54x
+ default 1
+
+config EBIU_FCTLVAL
+ hex "Flash Memory Bank Control Register"
+ depends on BF54x
+ default 6
endmenu
#############################################################################
config PCI
bool "PCI support"
+ depends on BROKEN
help
Support for PCI bus.
plugged into slots found on all modern laptop computers. Another
example, used on modern desktops as well as laptops, is USB.
- Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
- software (at <http://linux-hotplug.sourceforge.net/>) and install it.
+ Enable HOTPLUG and build a modular kernel. Get agent software
+ (from <http://linux-hotplug.sourceforge.net/>) and install it.
Then your kernel will automatically call out to a user mode "policy
agent" (/sbin/hotplug) to load modules and set up software needed
to use devices as you hotplug them.
menu "Power management options"
source "kernel/power/Kconfig"
+config ARCH_SUSPEND_POSSIBLE
+ def_bool y
+ depends on !SMP
+
choice
- prompt "Select PM Wakeup Event Source"
- default PM_WAKEUP_GPIO_BY_SIC_IWR
+ prompt "Standby Power Saving Mode"
depends on PM
+ default PM_BFIN_SLEEP_DEEPER
+config PM_BFIN_SLEEP_DEEPER
+ bool "Sleep Deeper"
help
- If you have a GPIO already configured as input with the corresponding PORTx_MASK
- bit set - "Specify Wakeup Event by SIC_IWR value"
-
-config PM_WAKEUP_GPIO_BY_SIC_IWR
- bool "Specify Wakeup Event by SIC_IWR value"
-config PM_WAKEUP_BY_GPIO
- bool "Cause Wakeup Event by GPIO"
-config PM_WAKEUP_GPIO_API
- bool "Configure Wakeup Event by PM GPIO API"
-
+ Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
+ power dissipation by disabling the clock to the processor core (CCLK).
+ Furthermore, Standby sets the internal power supply voltage (VDDINT)
+ to 0.85 V to provide the greatest power savings, while preserving the
+ processor state.
+ The PLL and system clock (SCLK) continue to operate at a very low
+ frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
+ the SDRAM is put into Self Refresh Mode. Typically an external event
+ such as GPIO interrupt or RTC activity wakes up the processor.
+ Various Peripherals such as UART, SPORT, PPI may not function as
+ normal during Sleep Deeper, due to the reduced SCLK frequency.
+ When in the sleep mode, system DMA access to L1 memory is not supported.
+
+ If unsure, select "Sleep Deeper".
+
+config PM_BFIN_SLEEP
+ bool "Sleep"
+ help
+ Sleep Mode (High Power Savings) - The sleep mode reduces power
+ dissipation by disabling the clock to the processor core (CCLK).
+ The PLL and system clock (SCLK), however, continue to operate in
+ this mode. Typically an external event or RTC activity will wake
+ up the processor. When in the sleep mode, system DMA access to L1
+ memory is not supported.
+
+ If unsure, select "Sleep Deeper".
endchoice
-config PM_WAKEUP_SIC_IWR
- hex "Wakeup Events (SIC_IWR)"
- depends on PM_WAKEUP_GPIO_BY_SIC_IWR
- default 0x80000000 if (BF537 || BF536 || BF534)
- default 0x100000 if (BF533 || BF532 || BF531)
+config PM_WAKEUP_BY_GPIO
+ bool "Allow Wakeup from Standby by GPIO"
config PM_WAKEUP_GPIO_NUMBER
- int "Wakeup GPIO number"
+ int "GPIO number"
range 0 47
depends on PM_WAKEUP_BY_GPIO
- default 2 if BFIN537_STAMP
+ default 2
choice
prompt "GPIO Polarity"
bool "Both EDGE"
endchoice
-endmenu
+comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
+ depends on PM
-if (BF537 || BF533 || BF54x)
+config PM_BFIN_WAKE_PH6
+ bool "Allow Wake-Up from on-chip PHY or PH6 GP"
+ depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
+ default n
+ help
+ Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
+
+config PM_BFIN_WAKE_GP
+ bool "Allow Wake-Up from GPIOs"
+ depends on PM && BF54x
+ default n
+ help
+ Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
+endmenu
menu "CPU Frequency scaling"
source "drivers/cpufreq/Kconfig"
-config CPU_FREQ
+config BFIN_CPU_FREQ
bool
+ depends on CPU_FREQ
+ select CPU_FREQ_TABLE
+ default y
+
+config CPU_VOLTAGE
+ bool "CPU Voltage scaling"
+ depends on EXPERIMENTAL
+ depends on CPU_FREQ
default n
help
- If you want to enable this option, you should select the
- DPMC driver from Character Devices.
-endmenu
+ Say Y here if you want CPU voltage scaling according to the CPU frequency.
+ This option violates the PLL BYPASS recommendation in the Blackfin Processor
+ manuals. There is a theoretical risk that during VDDINT transitions
+ the PLL may unlock.
-endif
+endmenu
source "net/Kconfig"
source "fs/Kconfig"
-source "kernel/Kconfig.instrumentation"
-
source "arch/blackfin/Kconfig.debug"
source "security/Kconfig"
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff