Blackfin arch: remove hardware PM code, oprofile not use it

[safe/jmp/linux-2.6] / arch / blackfin / Kconfig

diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 72ff719..56ee44d 100644 (file)
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -60,10 +60,6 @@ config GENERIC_CALIBRATE_DELAY
        bool
        default y
 
-config HARDWARE_PM
-       def_bool y
-       depends on OPROFILE
-
 source "init/Kconfig"
 
 source "kernel/Kconfig.preempt"
@@ -372,6 +368,7 @@ config BOOT_LOAD
 
 config ROM_BASE
        hex "Kernel ROM Base"
+       depends on ROMKERNEL
        default "0x20040000"
        range 0x20000000 0x20400000 if !(BF54x || BF561)
        range 0x20000000 0x30000000 if (BF54x || BF561)
@@ -472,13 +469,60 @@ config MEM_MT46V32M16_5B
        bool "MT46V32M16_5B"
 endchoice
 
-config MAX_MEM_SIZE
-       int "Max SDRAM Memory Size in MBytes"
-       depends on !MPU
-       default 512
+choice
+       prompt "DDR/SDRAM Timing"
+       depends on BFIN_KERNEL_CLOCK
+       default BFIN_KERNEL_CLOCK_MEMINIT_CALC
+       help
+         This option allows you to specify Blackfin SDRAM/DDR Timing parameters
+         The calculated SDRAM timing parameters may not be 100%
+         accurate - This option is therefore marked experimental.
+
+config BFIN_KERNEL_CLOCK_MEMINIT_CALC
+       bool "Calculate Timings (EXPERIMENTAL)"
+       depends on EXPERIMENTAL
+
+config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
+       bool "Provide accurate Timings based on target SCLK"
        help
-         This is the max memory size that the kernel will create CPLB
-         tables for.  Your system will not be able to handle any more.
+         Please consult the Blackfin Hardware Reference Manuals as well
+         as the memory device datasheet.
+         http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
+endchoice
+
+menu "Memory Init Control"
+       depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
+
+config MEM_DDRCTL0
+       depends on BF54x
+       hex "DDRCTL0"
+       default 0x0
+
+config MEM_DDRCTL1
+       depends on BF54x
+       hex "DDRCTL1"
+       default 0x0
+
+config MEM_DDRCTL2
+       depends on BF54x
+       hex "DDRCTL2"
+       default 0x0
+
+config MEM_EBIU_DDRQUE
+       depends on BF54x
+       hex "DDRQUE"
+       default 0x0
+
+config MEM_SDRRC
+       depends on !BF54x
+       hex "SDRRC"
+       default 0x0
+
+config MEM_SDGCTL
+       depends on !BF54x
+       hex "SDGCTL"
+       default 0x0
+endmenu
 
 #
 # Max & Min Speeds for various Chips
@@ -865,7 +909,7 @@ endchoice
 
 config BFIN_L2_CACHEABLE
        bool "Cache L2 SRAM"
-       depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
+       depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
        default n
        help
          Select to make L2 SRAM cacheable in L1 data and instruction cache.
@@ -1103,13 +1147,13 @@ config BFIN_CPU_FREQ
 
 config CPU_VOLTAGE
        bool "CPU Voltage scaling"
-       depends on EXPERIMENTAL 
+       depends on EXPERIMENTAL
        depends on CPU_FREQ
        default n
        help
          Say Y here if you want CPU voltage scaling according to the CPU frequency.
          This option violates the PLL BYPASS recommendation in the Blackfin Processor
-         manuals. There is a theoretical risk that during VDDINT transitions 
+         manuals. There is a theoretical risk that during VDDINT transitions
          the PLL may unlock.
 
 endmenu