* published by the Free Software Foundation.
*/
#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dw_dmac.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
#include <linux/spi/spi.h>
+#include <linux/usb/atmel_usba_udc.h>
+
+#include <mach/atmel-mci.h>
+#include <linux/atmel-mci.h>
#include <asm/io.h>
#include <asm/irq.h>
-#include <asm/arch/at32ap700x.h>
-#include <asm/arch/board.h>
-#include <asm/arch/portmux.h>
+#include <mach/at32ap700x.h>
+#include <mach/board.h>
+#include <mach/hmatrix.h>
+#include <mach/portmux.h>
+#include <mach/sram.h>
+
+#include <sound/atmel-abdac.h>
+#include <sound/atmel-ac97c.h>
#include <video/atmel_lcdc.h>
#include "clock.h"
-#include "hmatrix.h"
#include "pio.h"
#include "pm.h"
* don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
*/
#define DEFINE_DEV(_name, _id) \
-static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
+static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
static struct platform_device _name##_id##_device = { \
.name = #_name, \
.id = _id, \
.dev = { \
.dma_mask = &_name##_id##_dma_mask, \
- .coherent_dma_mask = DMA_32BIT_MASK, \
+ .coherent_dma_mask = DMA_BIT_MASK(32), \
}, \
.resource = _name##_id##_resource, \
.num_resources = ARRAY_SIZE(_name##_id##_resource), \
}
#define DEFINE_DEV_DATA(_name, _id) \
-static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
+static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
static struct platform_device _name##_id##_device = { \
.name = #_name, \
.id = _id, \
.dev = { \
.dma_mask = &_name##_id##_dma_mask, \
.platform_data = &_name##_id##_data, \
- .coherent_dma_mask = DMA_32BIT_MASK, \
+ .coherent_dma_mask = DMA_BIT_MASK(32), \
}, \
.resource = _name##_id##_resource, \
.num_resources = ARRAY_SIZE(_name##_id##_resource), \
}
-#define select_peripheral(pin, periph, flags) \
- at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
+#define select_peripheral(port, pin_mask, periph, flags) \
+ at32_select_periph(GPIO_##port##_BASE, pin_mask, \
+ GPIO_##periph, flags)
#define DEV_CLK(_name, devname, bus, _index) \
static struct clk devname##_##_name = { \
static DEFINE_SPINLOCK(pm_lock);
-unsigned long at32ap7000_osc_rates[3] = {
- [0] = 32768,
- /* FIXME: these are ATSTK1002-specific */
- [1] = 20000000,
- [2] = 12000000,
-};
+static struct clk osc0;
+static struct clk osc1;
static unsigned long osc_get_rate(struct clk *clk)
{
- return at32ap7000_osc_rates[clk->index];
+ return at32_board_osc_rates[clk->index];
}
static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
{
unsigned long div, mul, rate;
- if (!(control & PM_BIT(PLLEN)))
- return 0;
-
div = PM_BFEXT(PLLDIV, control) + 1;
mul = PM_BFEXT(PLLMUL, control) + 1;
return rate;
}
+static long pll_set_rate(struct clk *clk, unsigned long rate,
+ u32 *pll_ctrl)
+{
+ unsigned long mul;
+ unsigned long mul_best_fit = 0;
+ unsigned long div;
+ unsigned long div_min;
+ unsigned long div_max;
+ unsigned long div_best_fit = 0;
+ unsigned long base;
+ unsigned long pll_in;
+ unsigned long actual = 0;
+ unsigned long rate_error;
+ unsigned long rate_error_prev = ~0UL;
+ u32 ctrl;
+
+ /* Rate must be between 80 MHz and 200 Mhz. */
+ if (rate < 80000000UL || rate > 200000000UL)
+ return -EINVAL;
+
+ ctrl = PM_BF(PLLOPT, 4);
+ base = clk->parent->get_rate(clk->parent);
+
+ /* PLL input frequency must be between 6 MHz and 32 MHz. */
+ div_min = DIV_ROUND_UP(base, 32000000UL);
+ div_max = base / 6000000UL;
+
+ if (div_max < div_min)
+ return -EINVAL;
+
+ for (div = div_min; div <= div_max; div++) {
+ pll_in = (base + div / 2) / div;
+ mul = (rate + pll_in / 2) / pll_in;
+
+ if (mul == 0)
+ continue;
+
+ actual = pll_in * mul;
+ rate_error = abs(actual - rate);
+
+ if (rate_error < rate_error_prev) {
+ mul_best_fit = mul;
+ div_best_fit = div;
+ rate_error_prev = rate_error;
+ }
+
+ if (rate_error == 0)
+ break;
+ }
+
+ if (div_best_fit == 0)
+ return -EINVAL;
+
+ ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
+ ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
+ ctrl |= PM_BF(PLLCOUNT, 16);
+
+ if (clk->parent == &osc1)
+ ctrl |= PM_BIT(PLLOSC);
+
+ *pll_ctrl = ctrl;
+
+ return actual;
+}
+
static unsigned long pll0_get_rate(struct clk *clk)
{
u32 control;
return pll_get_rate(clk, control);
}
+static void pll1_mode(struct clk *clk, int enabled)
+{
+ unsigned long timeout;
+ u32 status;
+ u32 ctrl;
+
+ ctrl = pm_readl(PLL1);
+
+ if (enabled) {
+ if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
+ pr_debug("clk %s: failed to enable, rate not set\n",
+ clk->name);
+ return;
+ }
+
+ ctrl |= PM_BIT(PLLEN);
+ pm_writel(PLL1, ctrl);
+
+ /* Wait for PLL lock. */
+ for (timeout = 10000; timeout; timeout--) {
+ status = pm_readl(ISR);
+ if (status & PM_BIT(LOCK1))
+ break;
+ udelay(10);
+ }
+
+ if (!(status & PM_BIT(LOCK1)))
+ printk(KERN_ERR "clk %s: timeout waiting for lock\n",
+ clk->name);
+ } else {
+ ctrl &= ~PM_BIT(PLLEN);
+ pm_writel(PLL1, ctrl);
+ }
+}
+
static unsigned long pll1_get_rate(struct clk *clk)
{
u32 control;
return pll_get_rate(clk, control);
}
+static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
+{
+ u32 ctrl = 0;
+ unsigned long actual_rate;
+
+ actual_rate = pll_set_rate(clk, rate, &ctrl);
+
+ if (apply) {
+ if (actual_rate != rate)
+ return -EINVAL;
+ if (clk->users > 0)
+ return -EBUSY;
+ pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
+ clk->name, rate, actual_rate);
+ pm_writel(PLL1, ctrl);
+ }
+
+ return actual_rate;
+}
+
+static int pll1_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 ctrl;
+
+ if (clk->users > 0)
+ return -EBUSY;
+
+ ctrl = pm_readl(PLL1);
+ WARN_ON(ctrl & PM_BIT(PLLEN));
+
+ if (parent == &osc0)
+ ctrl &= ~PM_BIT(PLLOSC);
+ else if (parent == &osc1)
+ ctrl |= PM_BIT(PLLOSC);
+ else
+ return -EINVAL;
+
+ pm_writel(PLL1, ctrl);
+ clk->parent = parent;
+
+ return 0;
+}
+
/*
* The AT32AP7000 has five primary clock sources: One 32kHz
* oscillator, two crystal oscillators and two PLLs.
};
static struct clk pll1 = {
.name = "pll1",
+ .mode = pll1_mode,
.get_rate = pll1_get_rate,
+ .set_rate = pll1_set_rate,
+ .set_parent = pll1_set_parent,
.parent = &osc0,
};
return bus_clk_get_rate(clk, shift);
}
-static void pba_clk_mode(struct clk *clk, int enabled)
+void pba_clk_mode(struct clk *clk, int enabled)
{
unsigned long flags;
u32 mask;
spin_unlock_irqrestore(&pm_lock, flags);
}
-static unsigned long pba_clk_get_rate(struct clk *clk)
+unsigned long pba_clk_get_rate(struct clk *clk)
{
unsigned long cksel, shift = 0;
clk->parent = parent;
}
+static struct dw_dma_platform_data dw_dmac0_data = {
+ .nr_channels = 3,
+};
+
+static struct resource dw_dmac0_resource[] = {
+ PBMEM(0xff200000),
+ IRQ(2),
+};
+DEFINE_DEV_DATA(dw_dmac, 0);
+DEV_CLK(hclk, dw_dmac0, hsb, 10);
+
/* --------------------------------------------------------------------
* System peripherals
* -------------------------------------------------------------------- */
.users = 1,
.index = 3,
};
+static struct clk sdramc_clk = {
+ .name = "sdramc_clk",
+ .parent = &pbb_clk,
+ .mode = pbb_clk_mode,
+ .get_rate = pbb_clk_get_rate,
+ .users = 1,
+ .index = 14,
+};
static struct resource smc0_resource[] = {
PBMEM(0xfff03400),
.users = 1,
};
-static struct resource dmaca0_resource[] = {
- {
- .start = 0xff200000,
- .end = 0xff20ffff,
- .flags = IORESOURCE_MEM,
- },
- IRQ(2),
-};
-DEFINE_DEV(dmaca, 0);
-DEV_CLK(hclk, dmaca0, hsb, 10);
-
/* --------------------------------------------------------------------
* HMATRIX
* -------------------------------------------------------------------- */
-static struct clk hmatrix_clk = {
+struct clk at32_hmatrix_clk = {
.name = "hmatrix_clk",
.parent = &pbb_clk,
.mode = pbb_clk_mode,
.index = 2,
.users = 1,
};
-#define HMATRIX_BASE ((void __iomem *)0xfff00800)
-
-#define hmatrix_readl(reg) \
- __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
-#define hmatrix_writel(reg,value) \
- __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
/*
* Set bits in the HMATRIX Special Function Register (SFR) used by the
*/
static inline void set_ebi_sfr_bits(u32 mask)
{
- u32 sfr;
-
- clk_enable(&hmatrix_clk);
- sfr = hmatrix_readl(SFR4);
- sfr |= mask;
- hmatrix_writel(SFR4, sfr);
- clk_disable(&hmatrix_clk);
+ hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
}
/* --------------------------------------------------------------------
- * System Timer/Counter (TC)
+ * Timer/Counter (TC)
* -------------------------------------------------------------------- */
-static struct resource at32_systc0_resource[] = {
+
+static struct resource at32_tcb0_resource[] = {
PBMEM(0xfff00c00),
IRQ(22),
};
-struct platform_device at32_systc0_device = {
- .name = "systc",
+static struct platform_device at32_tcb0_device = {
+ .name = "atmel_tcb",
.id = 0,
- .resource = at32_systc0_resource,
- .num_resources = ARRAY_SIZE(at32_systc0_resource),
+ .resource = at32_tcb0_resource,
+ .num_resources = ARRAY_SIZE(at32_tcb0_resource),
};
-DEV_CLK(pclk, at32_systc0, pbb, 3);
+DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
+
+static struct resource at32_tcb1_resource[] = {
+ PBMEM(0xfff01000),
+ IRQ(23),
+};
+static struct platform_device at32_tcb1_device = {
+ .name = "atmel_tcb",
+ .id = 1,
+ .resource = at32_tcb1_resource,
+ .num_resources = ARRAY_SIZE(at32_tcb1_resource),
+};
+DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
/* --------------------------------------------------------------------
* PIO
DEFINE_DEV(pio, 4);
DEV_CLK(mck, pio4, pba, 14);
-void __init at32_add_system_devices(void)
+static int __init system_device_init(void)
{
platform_device_register(&at32_pm0_device);
platform_device_register(&at32_intc0_device);
platform_device_register(&at32_eic0_device);
platform_device_register(&smc0_device);
platform_device_register(&pdc_device);
- platform_device_register(&dmaca0_device);
+ platform_device_register(&dw_dmac0_device);
- platform_device_register(&at32_systc0_device);
+ platform_device_register(&at32_tcb0_device);
+ platform_device_register(&at32_tcb1_device);
platform_device_register(&pio0_device);
platform_device_register(&pio1_device);
platform_device_register(&pio2_device);
platform_device_register(&pio3_device);
platform_device_register(&pio4_device);
+
+ return 0;
+}
+core_initcall(system_device_init);
+
+/* --------------------------------------------------------------------
+ * PSIF
+ * -------------------------------------------------------------------- */
+static struct resource atmel_psif0_resource[] __initdata = {
+ {
+ .start = 0xffe03c00,
+ .end = 0xffe03cff,
+ .flags = IORESOURCE_MEM,
+ },
+ IRQ(18),
+};
+static struct clk atmel_psif0_pclk = {
+ .name = "pclk",
+ .parent = &pba_clk,
+ .mode = pba_clk_mode,
+ .get_rate = pba_clk_get_rate,
+ .index = 15,
+};
+
+static struct resource atmel_psif1_resource[] __initdata = {
+ {
+ .start = 0xffe03d00,
+ .end = 0xffe03dff,
+ .flags = IORESOURCE_MEM,
+ },
+ IRQ(18),
+};
+static struct clk atmel_psif1_pclk = {
+ .name = "pclk",
+ .parent = &pba_clk,
+ .mode = pba_clk_mode,
+ .get_rate = pba_clk_get_rate,
+ .index = 15,
+};
+
+struct platform_device *__init at32_add_device_psif(unsigned int id)
+{
+ struct platform_device *pdev;
+ u32 pin_mask;
+
+ if (!(id == 0 || id == 1))
+ return NULL;
+
+ pdev = platform_device_alloc("atmel_psif", id);
+ if (!pdev)
+ return NULL;
+
+ switch (id) {
+ case 0:
+ pin_mask = (1 << 8) | (1 << 9); /* CLOCK & DATA */
+
+ if (platform_device_add_resources(pdev, atmel_psif0_resource,
+ ARRAY_SIZE(atmel_psif0_resource)))
+ goto err_add_resources;
+ atmel_psif0_pclk.dev = &pdev->dev;
+ select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
+ break;
+ case 1:
+ pin_mask = (1 << 11) | (1 << 12); /* CLOCK & DATA */
+
+ if (platform_device_add_resources(pdev, atmel_psif1_resource,
+ ARRAY_SIZE(atmel_psif1_resource)))
+ goto err_add_resources;
+ atmel_psif1_pclk.dev = &pdev->dev;
+ select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
+ break;
+ default:
+ return NULL;
+ }
+
+ platform_device_add(pdev);
+ return pdev;
+
+err_add_resources:
+ platform_device_put(pdev);
+ return NULL;
}
/* --------------------------------------------------------------------
DEFINE_DEV_DATA(atmel_usart, 3);
DEV_CLK(usart, atmel_usart3, pba, 6);
-static inline void configure_usart0_pins(void)
+static inline void configure_usart0_pins(int flags)
{
- select_peripheral(PA(8), PERIPH_B, 0); /* RXD */
- select_peripheral(PA(9), PERIPH_B, 0); /* TXD */
+ u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
+ if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 6);
+ if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 7);
+ if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 10);
+
+ select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
}
-static inline void configure_usart1_pins(void)
+static inline void configure_usart1_pins(int flags)
{
- select_peripheral(PA(17), PERIPH_A, 0); /* RXD */
- select_peripheral(PA(18), PERIPH_A, 0); /* TXD */
+ u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
+ if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 19);
+ if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 20);
+ if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 16);
+
+ select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP);
}
-static inline void configure_usart2_pins(void)
+static inline void configure_usart2_pins(int flags)
{
- select_peripheral(PB(26), PERIPH_B, 0); /* RXD */
- select_peripheral(PB(27), PERIPH_B, 0); /* TXD */
+ u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
+ if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 30);
+ if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 29);
+ if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 28);
+
+ select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
}
-static inline void configure_usart3_pins(void)
+static inline void configure_usart3_pins(int flags)
{
- select_peripheral(PB(18), PERIPH_B, 0); /* RXD */
- select_peripheral(PB(17), PERIPH_B, 0); /* TXD */
+ u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
+ if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 16);
+ if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 15);
+ if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 19);
+
+ select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
}
static struct platform_device *__initdata at32_usarts[4];
-void __init at32_map_usart(unsigned int hw_id, unsigned int line)
+void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags)
{
struct platform_device *pdev;
switch (hw_id) {
case 0:
pdev = &atmel_usart0_device;
- configure_usart0_pins();
+ configure_usart0_pins(flags);
break;
case 1:
pdev = &atmel_usart1_device;
- configure_usart1_pins();
+ configure_usart1_pins(flags);
break;
case 2:
pdev = &atmel_usart2_device;
- configure_usart2_pins();
+ configure_usart2_pins(flags);
break;
case 3:
pdev = &atmel_usart3_device;
- configure_usart3_pins();
+ configure_usart3_pins(flags);
break;
default:
return;
at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
{
struct platform_device *pdev;
+ u32 pin_mask;
switch (id) {
case 0:
pdev = &macb0_device;
- select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */
- select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */
- select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */
- select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */
- select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */
- select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
- select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
- select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
- select_peripheral(PC(16), PERIPH_A, 0); /* MDC */
- select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
+ pin_mask = (1 << 3); /* TXD0 */
+ pin_mask |= (1 << 4); /* TXD1 */
+ pin_mask |= (1 << 7); /* TXEN */
+ pin_mask |= (1 << 8); /* TXCK */
+ pin_mask |= (1 << 9); /* RXD0 */
+ pin_mask |= (1 << 10); /* RXD1 */
+ pin_mask |= (1 << 13); /* RXER */
+ pin_mask |= (1 << 15); /* RXDV */
+ pin_mask |= (1 << 16); /* MDC */
+ pin_mask |= (1 << 17); /* MDIO */
if (!data->is_rmii) {
- select_peripheral(PC(0), PERIPH_A, 0); /* COL */
- select_peripheral(PC(1), PERIPH_A, 0); /* CRS */
- select_peripheral(PC(2), PERIPH_A, 0); /* TXER */
- select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */
- select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */
- select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
- select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
- select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
- select_peripheral(PC(18), PERIPH_A, 0); /* SPD */
+ pin_mask |= (1 << 0); /* COL */
+ pin_mask |= (1 << 1); /* CRS */
+ pin_mask |= (1 << 2); /* TXER */
+ pin_mask |= (1 << 5); /* TXD2 */
+ pin_mask |= (1 << 6); /* TXD3 */
+ pin_mask |= (1 << 11); /* RXD2 */
+ pin_mask |= (1 << 12); /* RXD3 */
+ pin_mask |= (1 << 14); /* RXCK */
+#ifndef CONFIG_BOARD_MIMC200
+ pin_mask |= (1 << 18); /* SPD */
+#endif
}
+
+ select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
+
break;
case 1:
pdev = &macb1_device;
- select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
- select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
- select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
- select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
- select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
- select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
- select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
- select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
- select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
- select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
+ pin_mask = (1 << 13); /* TXD0 */
+ pin_mask |= (1 << 14); /* TXD1 */
+ pin_mask |= (1 << 11); /* TXEN */
+ pin_mask |= (1 << 12); /* TXCK */
+ pin_mask |= (1 << 10); /* RXD0 */
+ pin_mask |= (1 << 6); /* RXD1 */
+ pin_mask |= (1 << 5); /* RXER */
+ pin_mask |= (1 << 4); /* RXDV */
+ pin_mask |= (1 << 3); /* MDC */
+ pin_mask |= (1 << 2); /* MDIO */
+
+#ifndef CONFIG_BOARD_MIMC200
+ if (!data->is_rmii)
+ pin_mask |= (1 << 15); /* SPD */
+#endif
+
+ select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
if (!data->is_rmii) {
- select_peripheral(PC(19), PERIPH_B, 0); /* COL */
- select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
- select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
- select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
- select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
- select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
- select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
- select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
- select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
+ pin_mask = (1 << 19); /* COL */
+ pin_mask |= (1 << 23); /* CRS */
+ pin_mask |= (1 << 26); /* TXER */
+ pin_mask |= (1 << 27); /* TXD2 */
+ pin_mask |= (1 << 28); /* TXD3 */
+ pin_mask |= (1 << 29); /* RXD2 */
+ pin_mask |= (1 << 30); /* RXD3 */
+ pin_mask |= (1 << 24); /* RXCK */
+
+ select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
}
break;
DEFINE_DEV(atmel_spi, 1);
DEV_CLK(spi_clk, atmel_spi1, pba, 1);
-static void __init
-at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
- unsigned int n, const u8 *pins)
+void __init
+at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n)
{
+ /*
+ * Manage the chipselects as GPIOs, normally using the same pins
+ * the SPI controller expects; but boards can use other pins.
+ */
+ static u8 __initdata spi_pins[][4] = {
+ { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
+ GPIO_PIN_PA(5), GPIO_PIN_PA(20) },
+ { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
+ GPIO_PIN_PB(4), GPIO_PIN_PA(27) },
+ };
unsigned int pin, mode;
+ /* There are only 2 SPI controllers */
+ if (bus_num > 1)
+ return;
+
for (; n; n--, b++) {
b->bus_num = bus_num;
if (b->chip_select >= 4)
continue;
pin = (unsigned)b->controller_data;
if (!pin) {
- pin = pins[b->chip_select];
+ pin = spi_pins[bus_num][b->chip_select];
b->controller_data = (void *)pin;
}
mode = AT32_GPIOF_OUTPUT;
struct platform_device *__init
at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
{
- /*
- * Manage the chipselects as GPIOs, normally using the same pins
- * the SPI controller expects; but boards can use other pins.
- */
- static u8 __initdata spi0_pins[] =
- { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
- GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
- static u8 __initdata spi1_pins[] =
- { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
- GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
struct platform_device *pdev;
+ u32 pin_mask;
switch (id) {
case 0:
pdev = &atmel_spi0_device;
- select_peripheral(PA(0), PERIPH_A, 0); /* MISO */
- select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
- select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
- at32_spi_setup_slaves(0, b, n, spi0_pins);
+ pin_mask = (1 << 1) | (1 << 2); /* MOSI & SCK */
+
+ /* pullup MISO so a level is always defined */
+ select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
+ select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
+
+ at32_spi_setup_slaves(0, b, n);
break;
case 1:
pdev = &atmel_spi1_device;
- select_peripheral(PB(0), PERIPH_B, 0); /* MISO */
- select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
- select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
- at32_spi_setup_slaves(1, b, n, spi1_pins);
+ pin_mask = (1 << 1) | (1 << 5); /* MOSI */
+
+ /* pullup MISO so a level is always defined */
+ select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
+ select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
+
+ at32_spi_setup_slaves(1, b, n);
break;
default:
.index = 2,
};
-struct platform_device *__init at32_add_device_twi(unsigned int id)
+struct platform_device *__init at32_add_device_twi(unsigned int id,
+ struct i2c_board_info *b,
+ unsigned int n)
{
struct platform_device *pdev;
+ u32 pin_mask;
if (id != 0)
return NULL;
ARRAY_SIZE(atmel_twi0_resource)))
goto err_add_resources;
- select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
- select_peripheral(PA(7), PERIPH_A, 0); /* SDL */
+ pin_mask = (1 << 6) | (1 << 7); /* SDA & SDL */
+
+ select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
atmel_twi0_pclk.dev = &pdev->dev;
+ if (b)
+ i2c_register_board_info(id, b, n);
+
platform_device_add(pdev);
return pdev;
.index = 9,
};
-struct platform_device *__init at32_add_device_mci(unsigned int id)
+struct platform_device *__init
+at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
{
- struct platform_device *pdev;
+ struct platform_device *pdev;
+ struct mci_dma_data *slave;
+ u32 pioa_mask;
+ u32 piob_mask;
- if (id != 0)
+ if (id != 0 || !data)
+ return NULL;
+
+ /* Must have at least one usable slot */
+ if (!data->slot[0].bus_width && !data->slot[1].bus_width)
return NULL;
pdev = platform_device_alloc("atmel_mci", id);
if (!pdev)
- return NULL;
+ goto fail;
if (platform_device_add_resources(pdev, atmel_mci0_resource,
ARRAY_SIZE(atmel_mci0_resource)))
- goto err_add_resources;
+ goto fail;
+
+ slave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
+ if (!slave)
+ goto fail;
+
+ slave->sdata.dma_dev = &dw_dmac0_device.dev;
+ slave->sdata.reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
+ slave->sdata.cfg_hi = (DWC_CFGH_SRC_PER(0)
+ | DWC_CFGH_DST_PER(1));
+ slave->sdata.cfg_lo &= ~(DWC_CFGL_HS_DST_POL
+ | DWC_CFGL_HS_SRC_POL);
+
+ data->dma_slave = slave;
+
+ if (platform_device_add_data(pdev, data,
+ sizeof(struct mci_platform_data)))
+ goto fail_free;
+
+ /* CLK line is common to both slots */
+ pioa_mask = 1 << 10;
+
+ switch (data->slot[0].bus_width) {
+ case 4:
+ pioa_mask |= 1 << 13; /* DATA1 */
+ pioa_mask |= 1 << 14; /* DATA2 */
+ pioa_mask |= 1 << 15; /* DATA3 */
+ /* fall through */
+ case 1:
+ pioa_mask |= 1 << 11; /* CMD */
+ pioa_mask |= 1 << 12; /* DATA0 */
+
+ if (gpio_is_valid(data->slot[0].detect_pin))
+ at32_select_gpio(data->slot[0].detect_pin, 0);
+ if (gpio_is_valid(data->slot[0].wp_pin))
+ at32_select_gpio(data->slot[0].wp_pin, 0);
+ break;
+ case 0:
+ /* Slot is unused */
+ break;
+ default:
+ goto fail_free;
+ }
+
+ select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
+ piob_mask = 0;
+
+ switch (data->slot[1].bus_width) {
+ case 4:
+ piob_mask |= 1 << 8; /* DATA1 */
+ piob_mask |= 1 << 9; /* DATA2 */
+ piob_mask |= 1 << 10; /* DATA3 */
+ /* fall through */
+ case 1:
+ piob_mask |= 1 << 6; /* CMD */
+ piob_mask |= 1 << 7; /* DATA0 */
+ select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
+
+ if (gpio_is_valid(data->slot[1].detect_pin))
+ at32_select_gpio(data->slot[1].detect_pin, 0);
+ if (gpio_is_valid(data->slot[1].wp_pin))
+ at32_select_gpio(data->slot[1].wp_pin, 0);
+ break;
+ case 0:
+ /* Slot is unused */
+ break;
+ default:
+ if (!data->slot[0].bus_width)
+ goto fail_free;
- select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
- select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
- select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
- select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
- select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
- select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
+ data->slot[1].bus_width = 0;
+ break;
+ }
atmel_mci0_pclk.dev = &pdev->dev;
platform_device_add(pdev);
return pdev;
-err_add_resources:
+fail_free:
+ kfree(slave);
+fail:
+ data->dma_slave = NULL;
platform_device_put(pdev);
return NULL;
}
struct platform_device *__init
at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
- unsigned long fbmem_start, unsigned long fbmem_len)
+ unsigned long fbmem_start, unsigned long fbmem_len,
+ u64 pin_mask)
{
struct platform_device *pdev;
struct atmel_lcdfb_info *info;
struct fb_monspecs *monspecs;
struct fb_videomode *modedb;
unsigned int modedb_size;
+ u32 portc_mask, portd_mask, porte_mask;
/*
* Do a deep copy of the fb data, monspecs and modedb. Make
switch (id) {
case 0:
pdev = &atmel_lcdfb0_device;
- select_peripheral(PC(19), PERIPH_A, 0); /* CC */
- select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
- select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
- select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
- select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
- select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
- select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
- select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
- select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
- select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
- select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
- select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
- select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
- select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
- select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
- select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
- select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
- select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
- select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
- select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
- select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
- select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
- select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
- select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
- select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
- select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
- select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
- select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
- select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
- select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
- select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
+
+ if (pin_mask == 0ULL)
+ /* Default to "full" lcdc control signals and 24bit */
+ pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
+
+ /* LCDC on port C */
+ portc_mask = pin_mask & 0xfff80000;
+ select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
+
+ /* LCDC on port D */
+ portd_mask = pin_mask & 0x0003ffff;
+ select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
+
+ /* LCDC on port E */
+ porte_mask = (pin_mask >> 32) & 0x0007ffff;
+ select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
IRQ(24),
};
static struct clk atmel_pwm0_mck = {
- .name = "mck",
+ .name = "pwm_clk",
.parent = &pbb_clk,
.mode = pbb_clk_mode,
.get_rate = pbb_clk_get_rate,
struct platform_device *__init at32_add_device_pwm(u32 mask)
{
struct platform_device *pdev;
+ u32 pin_mask;
if (!mask)
return NULL;
if (platform_device_add_data(pdev, &mask, sizeof(mask)))
goto out_free_pdev;
+ pin_mask = 0;
if (mask & (1 << 0))
- select_peripheral(PA(28), PERIPH_A, 0);
+ pin_mask |= (1 << 28);
if (mask & (1 << 1))
- select_peripheral(PA(29), PERIPH_A, 0);
+ pin_mask |= (1 << 29);
+ if (pin_mask > 0)
+ select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
+
+ pin_mask = 0;
if (mask & (1 << 2))
- select_peripheral(PA(21), PERIPH_B, 0);
+ pin_mask |= (1 << 21);
if (mask & (1 << 3))
- select_peripheral(PA(22), PERIPH_B, 0);
+ pin_mask |= (1 << 22);
+ if (pin_mask > 0)
+ select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
atmel_pwm0_mck.dev = &pdev->dev;
at32_add_device_ssc(unsigned int id, unsigned int flags)
{
struct platform_device *pdev;
+ u32 pin_mask = 0;
switch (id) {
case 0:
pdev = &ssc0_device;
if (flags & ATMEL_SSC_RF)
- select_peripheral(PA(21), PERIPH_A, 0); /* RF */
+ pin_mask |= (1 << 21); /* RF */
if (flags & ATMEL_SSC_RK)
- select_peripheral(PA(22), PERIPH_A, 0); /* RK */
+ pin_mask |= (1 << 22); /* RK */
if (flags & ATMEL_SSC_TK)
- select_peripheral(PA(23), PERIPH_A, 0); /* TK */
+ pin_mask |= (1 << 23); /* TK */
if (flags & ATMEL_SSC_TF)
- select_peripheral(PA(24), PERIPH_A, 0); /* TF */
+ pin_mask |= (1 << 24); /* TF */
if (flags & ATMEL_SSC_TD)
- select_peripheral(PA(25), PERIPH_A, 0); /* TD */
+ pin_mask |= (1 << 25); /* TD */
if (flags & ATMEL_SSC_RD)
- select_peripheral(PA(26), PERIPH_A, 0); /* RD */
+ pin_mask |= (1 << 26); /* RD */
+
+ if (pin_mask > 0)
+ select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
+
break;
case 1:
pdev = &ssc1_device;
if (flags & ATMEL_SSC_RF)
- select_peripheral(PA(0), PERIPH_B, 0); /* RF */
+ pin_mask |= (1 << 0); /* RF */
if (flags & ATMEL_SSC_RK)
- select_peripheral(PA(1), PERIPH_B, 0); /* RK */
+ pin_mask |= (1 << 1); /* RK */
if (flags & ATMEL_SSC_TK)
- select_peripheral(PA(2), PERIPH_B, 0); /* TK */
+ pin_mask |= (1 << 2); /* TK */
if (flags & ATMEL_SSC_TF)
- select_peripheral(PA(3), PERIPH_B, 0); /* TF */
+ pin_mask |= (1 << 3); /* TF */
if (flags & ATMEL_SSC_TD)
- select_peripheral(PA(4), PERIPH_B, 0); /* TD */
+ pin_mask |= (1 << 4); /* TD */
if (flags & ATMEL_SSC_RD)
- select_peripheral(PA(5), PERIPH_B, 0); /* RD */
+ pin_mask |= (1 << 5); /* RD */
+
+ if (pin_mask > 0)
+ select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
+
break;
case 2:
pdev = &ssc2_device;
if (flags & ATMEL_SSC_TD)
- select_peripheral(PB(13), PERIPH_A, 0); /* TD */
+ pin_mask |= (1 << 13); /* TD */
if (flags & ATMEL_SSC_RD)
- select_peripheral(PB(14), PERIPH_A, 0); /* RD */
+ pin_mask |= (1 << 14); /* RD */
if (flags & ATMEL_SSC_TK)
- select_peripheral(PB(15), PERIPH_A, 0); /* TK */
+ pin_mask |= (1 << 15); /* TK */
if (flags & ATMEL_SSC_TF)
- select_peripheral(PB(16), PERIPH_A, 0); /* TF */
+ pin_mask |= (1 << 16); /* TF */
if (flags & ATMEL_SSC_RF)
- select_peripheral(PB(17), PERIPH_A, 0); /* RF */
+ pin_mask |= (1 << 17); /* RF */
if (flags & ATMEL_SSC_RK)
- select_peripheral(PB(18), PERIPH_A, 0); /* RK */
+ pin_mask |= (1 << 18); /* RK */
+
+ if (pin_mask > 0)
+ select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
+
break;
default:
return NULL;
.index = 6,
};
+#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
+ [idx] = { \
+ .name = nam, \
+ .index = idx, \
+ .fifo_size = maxpkt, \
+ .nr_banks = maxbk, \
+ .can_dma = dma, \
+ .can_isoc = isoc, \
+ }
+
+static struct usba_ep_data at32_usba_ep[] __initdata = {
+ EP("ep0", 0, 64, 1, 0, 0),
+ EP("ep1", 1, 512, 2, 1, 1),
+ EP("ep2", 2, 512, 2, 1, 1),
+ EP("ep3-int", 3, 64, 3, 1, 0),
+ EP("ep4-int", 4, 64, 3, 1, 0),
+ EP("ep5", 5, 1024, 3, 1, 1),
+ EP("ep6", 6, 1024, 3, 1, 1),
+};
+
+#undef EP
+
struct platform_device *__init
at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
{
+ /*
+ * pdata doesn't have room for any endpoints, so we need to
+ * append room for the ones we need right after it.
+ */
+ struct {
+ struct usba_platform_data pdata;
+ struct usba_ep_data ep[7];
+ } usba_data;
struct platform_device *pdev;
if (id != 0)
goto out_free_pdev;
if (data) {
- if (platform_device_add_data(pdev, data, sizeof(*data)))
- goto out_free_pdev;
-
- if (data->vbus_pin != GPIO_PIN_NONE)
- at32_select_gpio(data->vbus_pin, 0);
+ usba_data.pdata.vbus_pin = data->vbus_pin;
+ usba_data.pdata.vbus_pin_inverted = data->vbus_pin_inverted;
+ } else {
+ usba_data.pdata.vbus_pin = -EINVAL;
+ usba_data.pdata.vbus_pin_inverted = -EINVAL;
}
+ data = &usba_data.pdata;
+ data->num_ep = ARRAY_SIZE(at32_usba_ep);
+ memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
+
+ if (platform_device_add_data(pdev, data, sizeof(usba_data)))
+ goto out_free_pdev;
+
+ if (gpio_is_valid(data->vbus_pin))
+ at32_select_gpio(data->vbus_pin, 0);
+
usba0_pclk.dev = &pdev->dev;
usba0_hclk.dev = &pdev->dev;
unsigned int cs, unsigned int extint)
{
static unsigned int extint_pin_map[4] __initdata = {
- GPIO_PIN_PB(25),
- GPIO_PIN_PB(26),
- GPIO_PIN_PB(27),
- GPIO_PIN_PB(28),
+ (1 << 25),
+ (1 << 26),
+ (1 << 27),
+ (1 << 28),
};
static bool common_pins_initialized __initdata = false;
unsigned int extint_pin;
int ret;
+ u32 pin_mask;
if (extint >= ARRAY_SIZE(extint_pin_map))
return -EINVAL;
if (ret)
return ret;
- select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */
- set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
+ /* NCS4 -> OE_N */
+ select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
+ hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
break;
case 5:
ret = platform_device_add_resources(pdev,
if (ret)
return ret;
- select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */
- set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
+ /* NCS5 -> OE_N */
+ select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
+ hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
break;
default:
return -EINVAL;
}
if (!common_pins_initialized) {
- select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */
- select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */
- select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */
- select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */
+ pin_mask = (1 << 19); /* CFCE1 -> CS0_N */
+ pin_mask |= (1 << 20); /* CFCE2 -> CS1_N */
+ pin_mask |= (1 << 23); /* CFRNW -> DIR */
+ pin_mask |= (1 << 24); /* NWAIT <- IORDY */
+
+ select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
+
common_pins_initialized = true;
}
- at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
+ select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
pdev->resource[1].start = EIM_IRQ_BASE + extint;
pdev->resource[1].end = pdev->resource[1].start;
if (at32_init_ide_or_cf(pdev, data->cs, extint))
goto fail;
- if (data->detect_pin != GPIO_PIN_NONE)
+ if (gpio_is_valid(data->detect_pin))
at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
- if (data->reset_pin != GPIO_PIN_NONE)
+ if (gpio_is_valid(data->reset_pin))
at32_select_gpio(data->reset_pin, 0);
- if (data->vcc_pin != GPIO_PIN_NONE)
+ if (gpio_is_valid(data->vcc_pin))
at32_select_gpio(data->vcc_pin, 0);
/* READY is used as extint, so we can't select it as gpio */
#endif
/* --------------------------------------------------------------------
+ * NAND Flash / SmartMedia
+ * -------------------------------------------------------------------- */
+static struct resource smc_cs3_resource[] __initdata = {
+ {
+ .start = 0x0c000000,
+ .end = 0x0fffffff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = 0xfff03c00,
+ .end = 0xfff03fff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device *__init
+at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
+{
+ struct platform_device *pdev;
+
+ if (id != 0 || !data)
+ return NULL;
+
+ pdev = platform_device_alloc("atmel_nand", id);
+ if (!pdev)
+ goto fail;
+
+ if (platform_device_add_resources(pdev, smc_cs3_resource,
+ ARRAY_SIZE(smc_cs3_resource)))
+ goto fail;
+
+ if (platform_device_add_data(pdev, data,
+ sizeof(struct atmel_nand_data)))
+ goto fail;
+
+ hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
+ if (data->enable_pin)
+ at32_select_gpio(data->enable_pin,
+ AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
+ if (data->rdy_pin)
+ at32_select_gpio(data->rdy_pin, 0);
+ if (data->det_pin)
+ at32_select_gpio(data->det_pin, 0);
+
+ platform_device_add(pdev);
+ return pdev;
+
+fail:
+ platform_device_put(pdev);
+ return NULL;
+}
+
+/* --------------------------------------------------------------------
* AC97C
* -------------------------------------------------------------------- */
static struct resource atmel_ac97c0_resource[] __initdata = {
.index = 10,
};
-struct platform_device *__init at32_add_device_ac97c(unsigned int id)
+struct platform_device *__init
+at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
+ unsigned int flags)
{
- struct platform_device *pdev;
+ struct platform_device *pdev;
+ struct dw_dma_slave *rx_dws;
+ struct dw_dma_slave *tx_dws;
+ struct ac97c_platform_data _data;
+ u32 pin_mask;
if (id != 0)
return NULL;
if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
ARRAY_SIZE(atmel_ac97c0_resource)))
- goto err_add_resources;
+ goto out_free_resources;
+
+ if (!data) {
+ data = &_data;
+ memset(data, 0, sizeof(struct ac97c_platform_data));
+ data->reset_pin = -ENODEV;
+ }
+
+ rx_dws = &data->rx_dws;
+ tx_dws = &data->tx_dws;
+
+ /* Check if DMA slave interface for capture should be configured. */
+ if (flags & AC97C_CAPTURE) {
+ rx_dws->dma_dev = &dw_dmac0_device.dev;
+ rx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
+ rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3);
+ rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
+ }
+
+ /* Check if DMA slave interface for playback should be configured. */
+ if (flags & AC97C_PLAYBACK) {
+ tx_dws->dma_dev = &dw_dmac0_device.dev;
+ tx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
+ tx_dws->cfg_hi = DWC_CFGH_DST_PER(4);
+ tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
+ }
+
+ if (platform_device_add_data(pdev, data,
+ sizeof(struct ac97c_platform_data)))
+ goto out_free_resources;
+
+ /* SDO | SYNC | SCLK | SDI */
+ pin_mask = (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23);
- select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
- select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
- select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
- select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
+ select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
+
+ if (gpio_is_valid(data->reset_pin))
+ at32_select_gpio(data->reset_pin, AT32_GPIOF_OUTPUT
+ | AT32_GPIOF_HIGH);
atmel_ac97c0_pclk.dev = &pdev->dev;
platform_device_add(pdev);
return pdev;
-err_add_resources:
+out_free_resources:
platform_device_put(pdev);
return NULL;
}
.index = 6,
};
-struct platform_device *__init at32_add_device_abdac(unsigned int id)
+struct platform_device *__init
+at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
{
- struct platform_device *pdev;
+ struct platform_device *pdev;
+ struct dw_dma_slave *dws;
+ u32 pin_mask;
- if (id != 0)
+ if (id != 0 || !data)
return NULL;
- pdev = platform_device_alloc("abdac", id);
+ pdev = platform_device_alloc("atmel_abdac", id);
if (!pdev)
return NULL;
if (platform_device_add_resources(pdev, abdac0_resource,
ARRAY_SIZE(abdac0_resource)))
- goto err_add_resources;
+ goto out_free_resources;
+
+ dws = &data->dws;
+
+ dws->dma_dev = &dw_dmac0_device.dev;
+ dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
+ dws->cfg_hi = DWC_CFGH_DST_PER(2);
+ dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
+
+ if (platform_device_add_data(pdev, data,
+ sizeof(struct atmel_abdac_pdata)))
+ goto out_free_resources;
- select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
- select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
- select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
- select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
+ pin_mask = (1 << 20) | (1 << 22); /* DATA1 & DATAN1 */
+ pin_mask |= (1 << 21) | (1 << 23); /* DATA0 & DATAN0 */
+
+ select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
abdac0_pclk.dev = &pdev->dev;
abdac0_sample_clk.dev = &pdev->dev;
platform_device_add(pdev);
return pdev;
-err_add_resources:
+out_free_resources:
platform_device_put(pdev);
return NULL;
}
.index = 4,
};
-struct clk *at32_clock_list[] = {
+static __initdata struct clk *init_clocks[] = {
&osc32k,
&osc0,
&osc1,
&pbb_clk,
&at32_pm_pclk,
&at32_intc0_pclk,
- &hmatrix_clk,
+ &at32_hmatrix_clk,
&ebi_clk,
&hramc_clk,
+ &sdramc_clk,
&smc0_pclk,
&smc0_mck,
&pdc_hclk,
&pdc_pclk,
- &dmaca0_hclk,
+ &dw_dmac0_hclk,
&pico_clk,
&pio0_mck,
&pio1_mck,
&pio2_mck,
&pio3_mck,
&pio4_mck,
- &at32_systc0_pclk,
+ &at32_tcb0_t0_clk,
+ &at32_tcb1_t0_clk,
+ &atmel_psif0_pclk,
+ &atmel_psif1_pclk,
&atmel_usart0_usart,
&atmel_usart1_usart,
&atmel_usart2_usart,
&gclk3,
&gclk4,
};
-unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
-
-void __init at32_portmux_init(void)
-{
- at32_init_pio(&pio0_device);
- at32_init_pio(&pio1_device);
- at32_init_pio(&pio2_device);
- at32_init_pio(&pio3_device);
- at32_init_pio(&pio4_device);
-}
-void __init at32_clock_init(void)
+void __init setup_platform(void)
{
u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
int i;
genclk_init_parent(&abdac0_sample_clk);
/*
- * Turn on all clocks that have at least one user already, and
- * turn off everything else. We only do this for module
- * clocks, and even though it isn't particularly pretty to
- * check the address of the mode function, it should do the
- * trick...
+ * Build initial dynamic clock list by registering all clocks
+ * from the array.
+ * At the same time, turn on all clocks that have at least one
+ * user already, and turn off everything else. We only do this
+ * for module clocks, and even though it isn't particularly
+ * pretty to check the address of the mode function, it should
+ * do the trick...
*/
- for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
- struct clk *clk = at32_clock_list[i];
+ for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
+ struct clk *clk = init_clocks[i];
+
+ /* first, register clock */
+ at32_clk_register(clk);
if (clk->users == 0)
continue;
pm_writel(HSB_MASK, hsb_mask);
pm_writel(PBA_MASK, pba_mask);
pm_writel(PBB_MASK, pbb_mask);
+
+ /* Initialize the port muxes */
+ at32_init_pio(&pio0_device);
+ at32_init_pio(&pio1_device);
+ at32_init_pio(&pio2_device);
+ at32_init_pio(&pio3_device);
+ at32_init_pio(&pio4_device);
+}
+
+struct gen_pool *sram_pool;
+
+static int __init sram_init(void)
+{
+ struct gen_pool *pool;
+
+ /* 1KiB granularity */
+ pool = gen_pool_create(10, -1);
+ if (!pool)
+ goto fail;
+
+ if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
+ goto err_pool_add;
+
+ sram_pool = pool;
+ return 0;
+
+err_pool_add:
+ gen_pool_destroy(pool);
+fail:
+ pr_err("Failed to create SRAM pool\n");
+ return -ENOMEM;
}
+core_initcall(sram_init);
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff