ARM: add size argument to __cpuc_flush_dcache_page

[safe/jmp/linux-2.6] / arch / arm / mm / proc-feroceon.S

diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index 63ca1ea..dbc3938 100644 (file)
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -22,7 +22,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
@@ -80,7 +80,8 @@ ENTRY(cpu_feroceon_proc_fin)
        msr     cpsr_c, ip
        bl      feroceon_flush_kern_cache_all
 
-#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && \
+       !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
        mov     r0, #0
        mcr     p15, 1, r0, c15, c9, 0          @ clean L2
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
@@ -225,16 +226,17 @@ ENTRY(feroceon_coherent_user_range)
        mov     pc, lr
 
 /*
- *     flush_kern_dcache_page(void *page)
+ *     flush_kern_dcache_area(void *addr, size_t size)
  *
  *     Ensure no D cache aliasing occurs, either with itself or
  *     the I cache
  *
- *     - addr  - page aligned address
+ *     - addr  - kernel address
+ *     - size  - region size
  */
        .align  5
-ENTRY(feroceon_flush_kern_dcache_page)
-       add     r1, r0, #PAGE_SZ
+ENTRY(feroceon_flush_kern_dcache_area)
+       add     r1, r0, r1
 1:     mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
        add     r0, r0, #CACHE_DLINESIZE
        cmp     r0, r1
@@ -245,7 +247,7 @@ ENTRY(feroceon_flush_kern_dcache_page)
        mov     pc, lr
 
        .align  5
-ENTRY(feroceon_range_flush_kern_dcache_page)
+ENTRY(feroceon_range_flush_kern_dcache_area)
        mrs     r2, cpsr
        add     r1, r0, #PAGE_SZ - CACHE_DLINESIZE      @ top addr is inclusive
        orr     r3, r2, #PSR_I_BIT
@@ -371,7 +373,7 @@ ENTRY(feroceon_cache_fns)
        .long   feroceon_flush_user_cache_range
        .long   feroceon_coherent_kern_range
        .long   feroceon_coherent_user_range
-       .long   feroceon_flush_kern_dcache_page
+       .long   feroceon_flush_kern_dcache_area
        .long   feroceon_dma_inv_range
        .long   feroceon_dma_clean_range
        .long   feroceon_dma_flush_range
@@ -382,14 +384,15 @@ ENTRY(feroceon_range_cache_fns)
        .long   feroceon_flush_user_cache_range
        .long   feroceon_coherent_kern_range
        .long   feroceon_coherent_user_range
-       .long   feroceon_range_flush_kern_dcache_page
+       .long   feroceon_range_flush_kern_dcache_area
        .long   feroceon_range_dma_inv_range
        .long   feroceon_range_dma_clean_range
        .long   feroceon_range_dma_flush_range
 
        .align  5
 ENTRY(cpu_feroceon_dcache_clean_area)
-#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && \
+       !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
        mov     r2, r0
        mov     r3, r1
 #endif
@@ -397,7 +400,8 @@ ENTRY(cpu_feroceon_dcache_clean_area)
        add     r0, r0, #CACHE_DLINESIZE
        subs    r1, r1, #CACHE_DLINESIZE
        bhi     1b
-#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && \
+       !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
 1:     mcr     p15, 1, r2, c15, c9, 1          @ clean L2 entry
        add     r2, r2, #CACHE_DLINESIZE
        subs    r3, r3, #CACHE_DLINESIZE
@@ -446,27 +450,11 @@ ENTRY(cpu_feroceon_switch_mm)
        .align  5
 ENTRY(cpu_feroceon_set_pte_ext)
 #ifdef CONFIG_MMU
-       str     r1, [r0], #-2048                @ linux version
-
-       eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-       bic     r2, r1, #PTE_SMALL_AP_MASK
-       bic     r2, r2, #PTE_TYPE_MASK
-       orr     r2, r2, #PTE_TYPE_SMALL
-
-       tst     r1, #L_PTE_USER                 @ User?
-       orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-       tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-       orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-       tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-       movne   r2, #0
-
-       str     r2, [r0]                        @ hardware version
+       armv3_set_pte_ext wc_disable=0
        mov     r0, r0
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
-#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && \
+       !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
        mcr     p15, 1, r0, c15, c9, 1          @ clean L2 entry
 #endif
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
@@ -493,14 +481,15 @@ __feroceon_setup:
        .size   __feroceon_setup, . - __feroceon_setup
 
        /*
-        *  R
-        * .RVI ZFRS BLDP WCAM
-        * .011 0001 ..11 0101
+        *      B
+        *  R   P
+        * .RVI UFRS BLDP WCAM
+        * .011 .001 ..11 0101
         *
         */
        .type   feroceon_crval, #object
 feroceon_crval:
-       crval   clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
+       crval   clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134
 
        __INITDATA
 
@@ -511,7 +500,7 @@ feroceon_crval:
        .type   feroceon_processor_functions, #object
 feroceon_processor_functions:
        .word   v5t_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_feroceon_proc_init
        .word   cpu_feroceon_proc_fin
        .word   cpu_feroceon_reset