* CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
*/
#include <linux/linkage.h>
-#include <linux/config.h>
#include <linux/init.h>
#include <asm/assembler.h>
+#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
-#include <asm/procinfo.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
mrc p15, 0, r1, c1, c0, 0 @ Read control register
mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
bic r2, r1, #1 << 12
+ mrs r3, cpsr @ Disable FIQs while Icache
+ orr ip, r3, #PSR_F_BIT @ is disabled
+ msr cpsr_c, ip
mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
+ msr cpsr_c, r3 @ Restore FIQ state
mov pc, lr
/*
mov pc, lr
/*
- * flush_kern_dcache_page(void *page)
+ * flush_kern_dcache_area(void *addr, size_t size)
*
* Ensure no D cache aliasing occurs, either with itself or
* the I cache
*
- * - addr - page aligned address
+ * - addr - kernel address
+ * - size - region size
*/
-ENTRY(arm926_flush_kern_dcache_page)
- add r1, r0, #PAGE_SZ
+ENTRY(arm926_flush_kern_dcache_area)
+ add r1, r0, r1
1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
*
* (same as v4wb)
*/
-ENTRY(arm926_dma_inv_range)
+arm926_dma_inv_range:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
tst r0, #CACHE_DLINESIZE - 1
mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
*
* (same as v4wb)
*/
-ENTRY(arm926_dma_clean_range)
+arm926_dma_clean_range:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
bic r0, r0, #CACHE_DLINESIZE - 1
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
#else
- mcr p15, 0, r0, c7, c10, 1 @ clean D entry
+ mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
#endif
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
mcr p15, 0, r0, c7, c10, 4 @ drain WB
mov pc, lr
+/*
+ * dma_map_area(start, size, dir)
+ * - start - kernel virtual start address
+ * - size - size of region
+ * - dir - DMA direction
+ */
+ENTRY(arm926_dma_map_area)
+ add r1, r1, r0
+ cmp r2, #DMA_TO_DEVICE
+ beq arm926_dma_clean_range
+ bcs arm926_dma_inv_range
+ b arm926_dma_flush_range
+ENDPROC(arm926_dma_map_area)
+
+/*
+ * dma_unmap_area(start, size, dir)
+ * - start - kernel virtual start address
+ * - size - size of region
+ * - dir - DMA direction
+ */
+ENTRY(arm926_dma_unmap_area)
+ mov pc, lr
+ENDPROC(arm926_dma_unmap_area)
+
ENTRY(arm926_cache_fns)
.long arm926_flush_kern_cache_all
.long arm926_flush_user_cache_all
.long arm926_flush_user_cache_range
.long arm926_coherent_kern_range
.long arm926_coherent_user_range
- .long arm926_flush_kern_dcache_page
- .long arm926_dma_inv_range
- .long arm926_dma_clean_range
+ .long arm926_flush_kern_dcache_area
+ .long arm926_dma_map_area
+ .long arm926_dma_unmap_area
.long arm926_dma_flush_range
ENTRY(cpu_arm926_dcache_clean_area)
mov pc, lr
/*
- * cpu_arm926_set_pte(ptep, pte)
+ * cpu_arm926_set_pte_ext(ptep, pte, ext)
*
* Set a PTE and flush it out
*/
.align 5
-ENTRY(cpu_arm926_set_pte)
+ENTRY(cpu_arm926_set_pte_ext)
#ifdef CONFIG_MMU
- str r1, [r0], #-2048 @ linux version
-
- eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
- bic r2, r1, #PTE_SMALL_AP_MASK
- bic r2, r2, #PTE_TYPE_MASK
- orr r2, r2, #PTE_TYPE_SMALL
-
- tst r1, #L_PTE_USER @ User?
- orrne r2, r2, #PTE_SMALL_AP_URO_SRW
-
- tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
- orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
-
- tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
- movne r2, #0
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
- eor r3, r2, #0x0a @ C & small page?
- tst r3, #0x0b
- biceq r2, r2, #4
-#endif
- str r2, [r0] @ hardware version
+ armv3_set_pte_ext
mov r0, r0
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
mcr p15, 7, r0, c15, c0, 0
#endif
+ adr r5, arm926_crval
+ ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register v4
- ldr r5, arm926_cr1_clear
bic r0, r0, r5
- ldr r5, arm926_cr1_set
- orr r0, r0, r5
+ orr r0, r0, r6
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .1.. .... .... ....
#endif
* .011 0001 ..11 0101
*
*/
- .type arm926_cr1_clear, #object
- .type arm926_cr1_set, #object
-arm926_cr1_clear:
- .word 0x7f3f
-arm926_cr1_set:
- .word 0x3135
+ .type arm926_crval, #object
+arm926_crval:
+ crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
__INITDATA
.type arm926_processor_functions, #object
arm926_processor_functions:
.word v5tj_early_abort
+ .word legacy_pabort
.word cpu_arm926_proc_init
.word cpu_arm926_proc_fin
.word cpu_arm926_reset
.word cpu_arm926_do_idle
.word cpu_arm926_dcache_clean_area
.word cpu_arm926_switch_mm
- .word cpu_arm926_set_pte
+ .word cpu_arm926_set_pte_ext
.size arm926_processor_functions, . - arm926_processor_functions
.section ".rodata"
.type cpu_arm926_name, #object
cpu_arm926_name:
- .ascii "ARM926EJ-S"
-#ifndef CONFIG_CPU_ICACHE_DISABLE
- .ascii "i"
-#endif
-#ifndef CONFIG_CPU_DCACHE_DISABLE
- .ascii "d"
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
- .ascii "(wt)"
-#else
- .ascii "(wb)"
-#endif
-#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
- .ascii "RR"
-#endif
-#endif
- .ascii "\0"
+ .asciz "ARM926EJ-S"
.size cpu_arm926_name, . - cpu_arm926_name
.align
PMD_BIT4 | \
PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ
+ .long PMD_TYPE_SECT | \
+ PMD_BIT4 | \
+ PMD_SECT_AP_WRITE | \
+ PMD_SECT_AP_READ
b __arm926_setup
.long cpu_arch_name
.long cpu_elf_name
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff