Merge branch 'for-rmk' of git://git.marvell.com/orion
[safe/jmp/linux-2.6] / arch / arm / mm / proc-arm720.S
index 26f00ee..85ae186 100644 (file)
@@ -4,6 +4,7 @@
  *  Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
  *                     Rob Scott (rscott@mtrob.fdns.net)
  *  Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
+ *  hacked for non-paged-MM by Hyok S. Choi, 2004.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  *                     out of 'proc-arm6,7.S' per RMK discussion
  *   07-25-2000 SJH    Added idle function.
  *   08-25-2000        DBS     Updated for integration of ARM Ltd version.
+ *   04-20-2004 HSC    modified for non-paged memory management mode.
  */
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
-#include <asm/procinfo.h>
 #include <asm/ptrace.h>
 
+#include "proc-macros.S"
+
 /*
  * Function: arm720_proc_init (void)
  *        : arm720_proc_fin (void)
@@ -75,39 +79,26 @@ ENTRY(cpu_arm720_do_idle)
  *          the new.
  */
 ENTRY(cpu_arm720_switch_mm)
+#ifdef CONFIG_MMU
                mov     r1, #0
                mcr     p15, 0, r1, c7, c7, 0           @ invalidate cache
                mcr     p15, 0, r0, c2, c0, 0           @ update page table ptr
                mcr     p15, 0, r1, c8, c7, 0           @ flush TLB (v4)
+#endif
                mov     pc, lr
 
 /*
- * Function: arm720_set_pte(pte_t *ptep, pte_t pte)
+ * Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
  * Params  : r0 = Address to set
  *        : r1 = value to set
  * Purpose : Set a PTE and flush it out of any WB cache
  */
-               .align  5
-ENTRY(cpu_arm720_set_pte)
-               str     r1, [r0], #-2048                @ linux version
-
-               eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-               bic     r2, r1, #PTE_SMALL_AP_MASK
-               bic     r2, r2, #PTE_TYPE_MASK
-               orr     r2, r2, #PTE_TYPE_SMALL
-
-               tst     r1, #L_PTE_USER                 @ User?
-               orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-               tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-               orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-               tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young
-               movne   r2, #0
-
-               str     r2, [r0]                        @ hardware version
-               mov     pc, lr
+       .align  5
+ENTRY(cpu_arm720_set_pte_ext)
+#ifdef CONFIG_MMU
+       armv3_set_pte_ext wc_disable=0
+#endif
+       mov     pc, lr
 
 /*
  * Function: arm720_reset
@@ -117,7 +108,9 @@ ENTRY(cpu_arm720_set_pte)
 ENTRY(cpu_arm720_reset)
                mov     ip, #0
                mcr     p15, 0, ip, c7, c7, 0           @ invalidate cache
+#ifdef CONFIG_MMU
                mcr     p15, 0, ip, c8, c7, 0           @ flush TLB (v4)
+#endif
                mrc     p15, 0, ip, c1, c0, 0           @ get ctrl register
                bic     ip, ip, #0x000f                 @ ............wcam
                bic     ip, ip, #0x2100                 @ ..v....s........
@@ -130,7 +123,9 @@ ENTRY(cpu_arm720_reset)
 __arm710_setup:
        mov     r0, #0
        mcr     p15, 0, r0, c7, c7, 0           @ invalidate caches
+#ifdef CONFIG_MMU
        mcr     p15, 0, r0, c8, c7, 0           @ flush TLB (v4)
+#endif
        mrc     p15, 0, r0, c1, c0              @ get control register
        ldr     r5, arm710_cr1_clear
        bic     r0, r0, r5
@@ -156,12 +151,14 @@ arm710_cr1_set:
 __arm720_setup:
        mov     r0, #0
        mcr     p15, 0, r0, c7, c7, 0           @ invalidate caches
+#ifdef CONFIG_MMU
        mcr     p15, 0, r0, c8, c7, 0           @ flush TLB (v4)
+#endif
+       adr     r5, arm720_crval
+       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0              @ get control register
-       ldr     r5, arm720_cr1_clear
        bic     r0, r0, r5
-       ldr     r5, arm720_cr1_set
-       orr     r0, r0, r5
+       orr     r0, r0, r6
        mov     pc, lr                          @ __ret (head.S)
        .size   __arm720_setup, . - __arm720_setup
 
@@ -171,12 +168,9 @@ __arm720_setup:
         * ..1. 1001 ..11 1101
         * 
         */
-       .type   arm720_cr1_clear, #object
-       .type   arm720_cr1_set, #object
-arm720_cr1_clear:
-       .word   0x2f3f
-arm720_cr1_set:
-       .word   0x213d
+       .type   arm720_crval, #object
+arm720_crval:
+       crval   clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
 
                __INITDATA
 
@@ -187,13 +181,14 @@ arm720_cr1_set:
                .type   arm720_processor_functions, #object
 ENTRY(arm720_processor_functions)
                .word   v4t_late_abort
+               .word   pabort_noifar
                .word   cpu_arm720_proc_init
                .word   cpu_arm720_proc_fin
                .word   cpu_arm720_reset
                .word   cpu_arm720_do_idle
                .word   cpu_arm720_dcache_clean_area
                .word   cpu_arm720_switch_mm
-               .word   cpu_arm720_set_pte
+               .word   cpu_arm720_set_pte_ext
                .size   arm720_processor_functions, . - arm720_processor_functions
 
                .section ".rodata"
@@ -219,7 +214,7 @@ cpu_arm720_name:
                .align
 
 /*
- * See linux/include/asm-arm/procinfo.h for a definition of this structure.
+ * See <asm/procinfo.h> for a definition of this structure.
  */
        
                .section ".proc.info.init", #alloc, #execinstr
@@ -234,6 +229,10 @@ __arm710_proc_info:
                        PMD_BIT4 | \
                        PMD_SECT_AP_WRITE | \
                        PMD_SECT_AP_READ
+               .long   PMD_TYPE_SECT | \
+                       PMD_BIT4 | \
+                       PMD_SECT_AP_WRITE | \
+                       PMD_SECT_AP_READ
                b       __arm710_setup                          @ cpu_flush
                .long   cpu_arch_name                           @ arch_name
                .long   cpu_elf_name                            @ elf_name
@@ -255,6 +254,10 @@ __arm720_proc_info:
                        PMD_BIT4 | \
                        PMD_SECT_AP_WRITE | \
                        PMD_SECT_AP_READ
+               .long   PMD_TYPE_SECT | \
+                       PMD_BIT4 | \
+                       PMD_SECT_AP_WRITE | \
+                       PMD_SECT_AP_READ
                b       __arm720_setup                          @ cpu_flush
                .long   cpu_arch_name                           @ arch_name
                .long   cpu_elf_name                            @ elf_name