[ARM] add Marvell 78xx0 ARM SoC support

[safe/jmp/linux-2.6] / arch / arm / mm / Kconfig

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index b1aa996..236603b 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -32,6 +32,7 @@ config CPU_ARM7TDMI
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_LV4T
+       select CPU_PABRT_NOIFAR
        select CPU_CACHE_V4
        help
          A 32-bit RISC microprocessor based on the ARM7 processor core
@@ -85,6 +86,7 @@ config CPU_ARM740T
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_LV4T
+       select CPU_PABRT_NOIFAR
        select CPU_CACHE_V3     # although the core is v4t
        select CPU_CP15_MPU
        help
@@ -101,6 +103,7 @@ config CPU_ARM9TDMI
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_NOMMU
+       select CPU_PABRT_NOIFAR
        select CPU_CACHE_V4
        help
          A 32-bit RISC microprocessor based on the ARM9 processor core
@@ -200,6 +203,7 @@ config CPU_ARM940T
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_NOMMU
+       select CPU_PABRT_NOIFAR
        select CPU_CACHE_VIVT
        select CPU_CP15_MPU
        help
@@ -217,6 +221,7 @@ config CPU_ARM946E
        depends on !MMU
        select CPU_32v5
        select CPU_ABRT_NOMMU
+       select CPU_PABRT_NOIFAR
        select CPU_CACHE_VIVT
        select CPU_CP15_MPU
        help
@@ -351,6 +356,7 @@ config CPU_XSC3
        default y
        select CPU_32v5
        select CPU_ABRT_EV5T
+       select CPU_PABRT_NOIFAR
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_TLB_V4WBI if MMU
@@ -359,15 +365,15 @@ config CPU_XSC3
 # Feroceon
 config CPU_FEROCEON
        bool
-       depends on ARCH_ORION
+       depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD || ARCH_MV78XX0
        default y
        select CPU_32v5
        select CPU_ABRT_EV5T
        select CPU_PABRT_NOIFAR
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
-       select CPU_COPY_V4WB if MMU
-       select CPU_TLB_V4WBI if MMU
+       select CPU_COPY_FEROCEON if MMU
+       select CPU_TLB_FEROCEON if MMU
 
 config CPU_FEROCEON_OLD_ID
        bool "Accept early Feroceon cores with an ARM926 ID"
@@ -381,7 +387,7 @@ config CPU_FEROCEON_OLD_ID
 # ARMv6
 config CPU_V6
        bool "Support ARM V6 processor"
-       depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A
+       depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
        default y if ARCH_MX3
        default y if ARCH_MSM7X00A
        select CPU_32v6
@@ -517,6 +523,9 @@ config CPU_COPY_V4WT
 config CPU_COPY_V4WB
        bool
 
+config CPU_COPY_FEROCEON
+       bool
+
 config CPU_COPY_V6
        bool
 
@@ -542,6 +551,11 @@ config CPU_TLB_V4WBI
          ARM Architecture Version 4 TLB with writeback cache and invalidate
          instruction cache entry.
 
+config CPU_TLB_FEROCEON
+       bool
+       help
+         Feroceon TLB (v4wbi with non-outer-cachable page table walks).
+
 config CPU_TLB_V6
        bool
 
@@ -652,7 +666,7 @@ config CPU_DCACHE_SIZE
 
 config CPU_DCACHE_WRITETHROUGH
        bool "Force write through D-cache"
-       depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FEROCEON) && !CPU_DCACHE_DISABLE
+       depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
        default y if CPU_ARM925T
        help
          Say Y here to use the data cache in writethrough mode. Unless you
@@ -700,6 +714,18 @@ config OUTER_CACHE
        bool
        default n
 
+config CACHE_FEROCEON_L2
+       bool "Enable the Feroceon L2 cache controller"
+       depends on ARCH_KIRKWOOD || ARCH_MV78XX0
+       default y
+       select OUTER_CACHE
+       help
+         This option enables the Feroceon L2 cache controller.
+
 config CACHE_L2X0
-       bool
+       bool "Enable the L2x0 outer cache controller"
+       depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
+       default y
        select OUTER_CACHE
+       help
+         This option enables the L2x0 PrimeCell.