Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial

[safe/jmp/linux-2.6] / arch / arm / mach-u300 / core.c

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 6869052..5f34eb6 100644 (file)
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -358,7 +358,7 @@ static struct resource ave_resources[] = {
        /*
         * The AVE3e requires two regions of 256MB that it considers
         * "invisible". The hardware will not be able to access these
-        * adresses, so they should never point to system RAM.
+        * addresses, so they should never point to system RAM.
         */
        {
                .name  = "AVE3e Reserved 0",
@@ -475,7 +475,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .priority_high = 0,
                .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
                                COH901318_CX_CFG_LCR_DISABLE |
                                COH901318_CX_CFG_TC_IRQ_ENABLE |
                                COH901318_CX_CFG_BE_IRQ_ENABLE,
@@ -528,7 +527,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .priority_high = 0,
                .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
                                COH901318_CX_CFG_LCR_DISABLE |
                                COH901318_CX_CFG_TC_IRQ_ENABLE |
                                COH901318_CX_CFG_BE_IRQ_ENABLE,
@@ -582,7 +580,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .priority_high = 0,
                .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
                                COH901318_CX_CFG_LCR_DISABLE |
                                COH901318_CX_CFG_TC_IRQ_ENABLE |
                                COH901318_CX_CFG_BE_IRQ_ENABLE,
@@ -635,7 +632,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .priority_high = 0,
                .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
                                COH901318_CX_CFG_LCR_DISABLE |
                                COH901318_CX_CFG_TC_IRQ_ENABLE |
                                COH901318_CX_CFG_BE_IRQ_ENABLE,
@@ -706,7 +702,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .priority_high = 0,
                .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
                                COH901318_CX_CFG_LCR_DISABLE |
                                COH901318_CX_CFG_TC_IRQ_ENABLE |
                                COH901318_CX_CFG_BE_IRQ_ENABLE,
@@ -746,7 +741,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .priority_high = 0,
                .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
                                COH901318_CX_CFG_LCR_DISABLE |
                                COH901318_CX_CFG_TC_IRQ_ENABLE |
                                COH901318_CX_CFG_BE_IRQ_ENABLE,
@@ -799,7 +793,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .priority_high = 0,
                .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
                                COH901318_CX_CFG_LCR_DISABLE |
                                COH901318_CX_CFG_TC_IRQ_ENABLE |
                                COH901318_CX_CFG_BE_IRQ_ENABLE,
@@ -852,7 +845,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .priority_high = 0,
                .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
                                COH901318_CX_CFG_LCR_DISABLE |
                                COH901318_CX_CFG_TC_IRQ_ENABLE |
                                COH901318_CX_CFG_BE_IRQ_ENABLE,
@@ -905,7 +897,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .priority_high = 0,
                .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
                                COH901318_CX_CFG_LCR_DISABLE |
                                COH901318_CX_CFG_TC_IRQ_ENABLE |
                                COH901318_CX_CFG_BE_IRQ_ENABLE,
@@ -964,7 +955,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .priority_high = 0,
                .dev_addr =  U300_MMCSD_BASE + 0x080,
                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
                                COH901318_CX_CFG_LCR_DISABLE |
                                COH901318_CX_CFG_TC_IRQ_ENABLE |
                                COH901318_CX_CFG_BE_IRQ_ENABLE,
@@ -974,8 +964,8 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_DISABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
                                COH901318_CX_CTRL_HSP_ENABLE |
                                COH901318_CX_CTRL_HSS_DISABLE |
                                COH901318_CX_CTRL_DDMA_LEGACY,
@@ -986,7 +976,7 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
                                COH901318_CX_CTRL_TCP_ENABLE |
-                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
                                COH901318_CX_CTRL_HSP_ENABLE |
                                COH901318_CX_CTRL_HSS_DISABLE |
                                COH901318_CX_CTRL_DDMA_LEGACY,
@@ -996,7 +986,7 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
-                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TCP_DISABLE |
                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
                                COH901318_CX_CTRL_HSP_ENABLE |
                                COH901318_CX_CTRL_HSS_DISABLE |
@@ -1039,7 +1029,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .priority_high = 1,
                .dev_addr = U300_PCM_I2S0_BASE + 0x14,
                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
                                COH901318_CX_CFG_LCR_DISABLE |
                                COH901318_CX_CFG_TC_IRQ_ENABLE |
                                COH901318_CX_CFG_BE_IRQ_ENABLE,
@@ -1092,7 +1081,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .priority_high = 1,
                .dev_addr = U300_PCM_I2S0_BASE + 0x10,
                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
                                COH901318_CX_CFG_LCR_DISABLE |
                                COH901318_CX_CFG_TC_IRQ_ENABLE |
                                COH901318_CX_CFG_BE_IRQ_ENABLE,
@@ -1145,7 +1133,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .priority_high = 1,
                .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY |
                                COH901318_CX_CFG_LCR_DISABLE |
                                COH901318_CX_CFG_TC_IRQ_ENABLE |
                                COH901318_CX_CFG_BE_IRQ_ENABLE,
@@ -1198,7 +1185,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
                .priority_high = 1,
                .dev_addr = U300_PCM_I2S1_BASE + 0x10,
                .param.config = COH901318_CX_CFG_CH_DISABLE |
-                               COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY |
                                COH901318_CX_CFG_LCR_DISABLE |
                                COH901318_CX_CFG_TC_IRQ_ENABLE |
                                COH901318_CX_CFG_BE_IRQ_ENABLE,
@@ -1610,7 +1596,7 @@ static void __init u300_init_check_chip(void)
 /*
  * Some devices and their resources require reserved physical memory from
  * the end of the available RAM. This function traverses the list of devices
- * and assigns actual adresses to these.
+ * and assigns actual addresses to these.
  */
 static void __init u300_assign_physmem(void)
 {