/*
- * STMP APBH Register Definitions
+ * stmp37xx: APBH register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-#ifndef _INCLUDE_ASM_ARCH_REGS_APBH_H
-#define _INCLUDE_ASM_ARCH_REGS_APBH_H
+#ifndef _MACH_REGS_APBH
+#define _MACH_REGS_APBH
-#include <mach/stmp3xxx_regs.h>
+#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000)
-#ifndef REGS_APBH_BASE
-#define REGS_APBH_BASE (REGS_BASE + 0x00004000)
-#endif
+#define HW_APBH_CTRL0 0x0
+#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
+#define BP_APBH_CTRL0_RESET_CHANNEL 16
+#define BM_APBH_CTRL0_CLKGATE 0x40000000
+#define BM_APBH_CTRL0_SFTRST 0x80000000
+
+#define HW_APBH_CTRL1 0x10
+#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
+#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
+
+#define HW_APBH_DEVSEL 0x20
+
+#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70)
+#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70)
+#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70)
+#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70)
+#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70)
+#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70)
+#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70)
+#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70)
+#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70)
+#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70)
+#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70)
+#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70)
+#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70)
+#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70)
+#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70)
+#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70)
-HW_REGISTER(HW_APBH_CTRL0, REGS_APBH_BASE, 0x00)
-#define BP_APBH_CTRL0_SFTRST 31
-#define BM_APBH_CTRL0_SFTRST 0x80000000
-#define BP_APBH_CTRL0_CLKGATE 30
-#define BM_APBH_CTRL0_CLKGATE 0x40000000
-#define BP_APBH_CTRL0_RESET_CHANNEL 16
-#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
-#define BF_APBH_CTRL0_RESET_CHANNEL(v) \
- (((v) << BP_APBH_CTRL0_RESET_CHANNEL) & BM_APBH_CTRL0_RESET_CHANNEL)
-HW_REGISTER(HW_APBH_CTRL1, REGS_APBH_BASE, 0x10)
-#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 9
-#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00000200
-#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 8
-#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00000100
-#define BP_APBH_CTRL1_CH7_CMDCMPLT_IRQ 7
-#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080
-#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ 1
-#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002
-#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
-#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
-#define BP_APBH_CTRL1_CH1_ERR_IRQ 17
-#define BM_APBH_CTRL1_CH1_ERR_IRQ 0x00020000
-HW_REGISTER_0(HW_APBH_DEVSEL, REGS_APBH_BASE, 0x20)
-HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CURCMDAR, REGS_APBH_BASE, 0x40, 0x70)
-HW_REGISTER_0_INDEXED(HW_APBH_CHn_NXTCMDAR, REGS_APBH_BASE, 0x50, 0x70)
-#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0
-#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF
-#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) ((u32) v)
-HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CMD, REGS_APBH_BASE, 0x60, 0x70)
-#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
-#define BP_APBH_CHn_CMD_XFER_COUNT 16
-#define BF_APBH_CHn_CMD_XFER_COUNT(v) \
- (((v) << BP_APBH_CHn_CMD_XFER_COUNT) & BM_APBH_CHn_CMD_XFER_COUNT)
-#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
-#define BP_APBH_CHn_CMD_CMDWORDS 12
-#define BF_APBH_CHn_CMD_CMDWORDS(v) \
- (((v) << BP_APBH_CHn_CMD_CMDWORDS) & BM_APBH_CHn_CMD_CMDWORDS)
-#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
-#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
-#define BP_APBH_CHn_CMD_SEMAPHORE 6
-#define BF_APBH_CHn_CMD_SEMAPHORE(v) \
- (((v) << BP_APBH_CHn_CMD_SEMAPHORE) & BM_APBH_CHn_CMD_SEMAPHORE)
-#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
-#define BP_APBH_CHn_CMD_NANDLOCK 4
-#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
-#define BF_APBH_CHn_CMD_NANDLOCK(v) \
- (((v) << BP_APBH_CHn_CMD_NANDLOCK) & BM_APBH_CHn_CMD_NANDLOCK)
-#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
+#define HW_APBH_CHn_NXTCMDAR 0x50
+
+#define BM_APBH_CHn_CMD_MODE 0x00000003
+#define BP_APBH_CHn_CMD_MODE 0x00000001
+#define BV_APBH_CHn_CMD_MODE_NOOP 0
+#define BV_APBH_CHn_CMD_MODE_WRITE 1
+#define BV_APBH_CHn_CMD_MODE_READ 2
+#define BV_APBH_CHn_CMD_MODE_SENSE 3
#define BM_APBH_CHn_CMD_CHAIN 0x00000004
-#define BM_APBH_CHn_CMD_DMA_READ 0x00000003
-#define BP_APBH_CHn_CMD_DMA_READ 0
-#define BF_APBH_CHn_CMD_DMA_READ(v) \
- (((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ)
-#define BF_APBH_CHn_CMD_COMMAND(v) \
- (((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ)
-#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0
-#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1
-#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2
-#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3
-HW_REGISTER_INDEXED(HW_APBH_CHn_BAR, REGS_APBH_BASE, 0x70, 0x70)
-HW_REGISTER_0_INDEXED(HW_APBH_CHn_SEMA, REGS_APBH_BASE, 0x80, 0x70)
-#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
-#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
-#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \
- (((v) << BP_APBH_CHn_SEMA_INCREMENT_SEMA) & \
- BM_APBH_CHn_SEMA_INCREMENT_SEMA)
-#define BP_APBH_CHn_SEMA_PHORE 16
-#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
-HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG1, REGS_APBH_BASE, 0x90, 0x70)
-HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG2, REGS_APBH_BASE, 0xA0, 0x70)
-HW_REGISTER_RO(HW_APBH_VERSION, REGS_APBH_BASE, 0x3F0)
+#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
+#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
+#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
+#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
+#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
+#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
+#define BP_APBH_CHn_CMD_CMDWORDS 12
+#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
+#define BP_APBH_CHn_CMD_XFER_COUNT 16
+
+#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70)
+#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70)
+#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70)
+#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70)
+#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70)
+#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70)
+#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70)
+#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70)
+#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70)
+#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70)
+#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70)
+#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70)
+#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70)
+#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70)
+#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70)
+#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70)
-#endif /* _INCLUDE_ASM_ARCH_REGS_APBH_H */
+#define HW_APBH_CHn_SEMA 0x80
+#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
+#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
+#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
+#define BP_APBH_CHn_SEMA_PHORE 16
+
+#endif
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff