arm/{pxa,sa1100,nomadik}: Don't disable irqs in set_next_event and set_mode

[safe/jmp/linux-2.6] / arch / arm / mach-pxa / time.c

diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 3c4abbf..293e40a 100644 (file)
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -17,13 +17,12 @@
 #include <linux/interrupt.h>
 #include <linux/clockchips.h>
 #include <linux/sched.h>
+#include <linux/cnt32_to_63.h>
 
 #include <asm/div64.h>
-#include <asm/cnt32_to_63.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/mach-types.h>
+#include <mach/regs-ost.h>
 
 /*
  * This is PXA's sched_clock implementation. This has a resolution
@@ -77,14 +76,12 @@ pxa_ost0_interrupt(int irq, void *dev_id)
 static int
 pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
 {
-       unsigned long flags, next, oscr;
+       unsigned long next, oscr;
 
-       raw_local_irq_save(flags);
        OIER |= OIER_E0;
        next = OSCR + delta;
        OSMR0 = next;
        oscr = OSCR;
-       raw_local_irq_restore(flags);
 
        return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
 }
@@ -92,23 +89,17 @@ pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
 static void
 pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 {
-       unsigned long irqflags;
-
        switch (mode) {
        case CLOCK_EVT_MODE_ONESHOT:
-               raw_local_irq_save(irqflags);
                OIER &= ~OIER_E0;
                OSSR = OSSR_M0;
-               raw_local_irq_restore(irqflags);
                break;
 
        case CLOCK_EVT_MODE_UNUSED:
        case CLOCK_EVT_MODE_SHUTDOWN:
                /* initializing, released, or preparing for suspend */
-               raw_local_irq_save(irqflags);
                OIER &= ~OIER_E0;
                OSSR = OSSR_M0;
-               raw_local_irq_restore(irqflags);
                break;
 
        case CLOCK_EVT_MODE_RESUME:
@@ -122,12 +113,11 @@ static struct clock_event_device ckevt_pxa_osmr0 = {
        .features       = CLOCK_EVT_FEAT_ONESHOT,
        .shift          = 32,
        .rating         = 200,
-       .cpumask        = CPU_MASK_CPU0,
        .set_next_event = pxa_osmr0_set_next_event,
        .set_mode       = pxa_osmr0_set_mode,
 };
 
-static cycle_t pxa_read_oscr(void)
+static cycle_t pxa_read_oscr(struct clocksource *cs)
 {
        return OSCR;
 }
@@ -150,18 +140,11 @@ static struct irqaction pxa_ost0_irq = {
 
 static void __init pxa_timer_init(void)
 {
-       unsigned long clock_tick_rate;
+       unsigned long clock_tick_rate = get_clock_tick_rate();
 
        OIER = 0;
        OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
 
-       if (cpu_is_pxa21x() || cpu_is_pxa25x())
-               clock_tick_rate = 3686400;
-       else if (machine_is_mainstone())
-               clock_tick_rate = 3249600;
-       else
-               clock_tick_rate = 3250000;
-
        set_oscr2ns_scale(clock_tick_rate);
 
        ckevt_pxa_osmr0.mult =
@@ -169,7 +152,8 @@ static void __init pxa_timer_init(void)
        ckevt_pxa_osmr0.max_delta_ns =
                clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
        ckevt_pxa_osmr0.min_delta_ns =
-               clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1;
+               clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
+       ckevt_pxa_osmr0.cpumask = cpumask_of(0);
 
        cksrc_pxa_oscr0.mult =
                clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift);
@@ -181,7 +165,7 @@ static void __init pxa_timer_init(void)
 }
 
 #ifdef CONFIG_PM
-static unsigned long osmr[4], oier;
+static unsigned long osmr[4], oier, oscr;
 
 static void pxa_timer_suspend(void)
 {
@@ -190,23 +174,26 @@ static void pxa_timer_suspend(void)
        osmr[2] = OSMR2;
        osmr[3] = OSMR3;
        oier = OIER;
+       oscr = OSCR;
 }
 
 static void pxa_timer_resume(void)
 {
+       /*
+        * Ensure that we have at least MIN_OSCR_DELTA between match
+        * register 0 and the OSCR, to guarantee that we will receive
+        * the one-shot timer interrupt.  We adjust OSMR0 in preference
+        * to OSCR to guarantee that OSCR is monotonically incrementing.
+        */
+       if (osmr[0] - oscr < MIN_OSCR_DELTA)
+               osmr[0] += MIN_OSCR_DELTA;
+
        OSMR0 = osmr[0];
        OSMR1 = osmr[1];
        OSMR2 = osmr[2];
        OSMR3 = osmr[3];
        OIER = oier;
-
-       /*
-        * OSCR0 is the system timer, which has to increase
-        * monotonically until it rolls over in hardware.  The value
-        * (OSMR0 - LATCH) is OSCR0 at the most recent system tick,
-        * which is a handy value to restore to OSCR0.
-        */
-       OSCR = OSMR0 - LATCH;
+       OSCR = oscr;
 }
 #else
 #define pxa_timer_suspend NULL