CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
+ CLK(NULL, "modem_fck", &modem_fck, CK_343X),
+ CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X),
+ CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X),
CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X),
CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
- CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X),
+ CLK("musb_hdrc", "ick", &hsotgusb_ick, CK_343X),
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
CLK("omap_rng", "ick", &rng_ick, CK_343X),
CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
CLK(NULL, "des1_ick", &des1_ick, CK_343X),
- CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X),
- CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X),
- CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X),
- CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X),
- CLK(NULL, "dss_ick", &dss_ick, CK_343X),
+ CLK("omapfb", "dss1_fck", &dss1_alwon_fck, CK_343X),
+ CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X),
+ CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X),
+ CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X),
+ CLK("omapfb", "ick", &dss_ick, CK_343X),
CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
CLK(NULL, "cam_ick", &cam_ick, CK_343X),
CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
#define MIN_SDRC_DLL_LOCK_FREQ 83000000
+#define CYCLES_PER_MHZ 1000000
+
+/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
+#define SDRC_MPURATE_SCALE 8
+
+/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
+#define SDRC_MPURATE_BASE_SHIFT 9
+
+/*
+ * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
+ * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
+ */
+#define SDRC_MPURATE_LOOPS 96
+
/**
* omap3_dpll_recalc - recalculate DPLL rate
* @clk: DPLL struct clk
{
u32 new_div = 0;
u32 unlock_dll = 0;
- unsigned long validrate, sdrcrate;
+ u32 c;
+ unsigned long validrate, sdrcrate, mpurate;
struct omap_sdrc_params *sp;
if (!clk || !rate)
if (clk != &dpll3_m2_ck)
return -EINVAL;
- if (rate == clk->rate)
- return 0;
-
validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
if (validrate != rate)
return -EINVAL;
sdrcrate = sdrc_ick.rate;
if (rate > clk->rate)
- sdrcrate <<= ((rate / clk->rate) - 1);
+ sdrcrate <<= ((rate / clk->rate) >> 1);
else
- sdrcrate >>= ((clk->rate / rate) - 1);
+ sdrcrate >>= ((clk->rate / rate) >> 1);
sp = omap2_sdrc_get_params(sdrcrate);
if (!sp)
unlock_dll = 1;
}
- pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
- validrate);
- pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
- sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
-
- /* REVISIT: SRAM code doesn't support other M2 divisors yet */
- WARN_ON(new_div != 1 && new_div != 2);
+ /*
+ * XXX This only needs to be done when the CPU frequency changes
+ */
+ mpurate = arm_fck.rate / CYCLES_PER_MHZ;
+ c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
+ c += 1; /* for safety */
+ c *= SDRC_MPURATE_LOOPS;
+ c >>= SDRC_MPURATE_SCALE;
+ if (c == 0)
+ c = 1;
+
+ pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
+ validrate);
+ pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
+ sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
- /* REVISIT: Add SDRC_MR changing to this code also */
omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
- sp->actim_ctrlb, new_div, unlock_dll);
+ sp->actim_ctrlb, new_div, unlock_dll, c,
+ sp->mr, rate > clk->rate);
return 0;
}
clk_init(&omap2_clk_functions);
for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
- clk_init_one(c->lk.clk);
+ clk_preinit(c->lk.clk);
for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
if (c->cpu & cpu_clkflg) {