Revert "[CPUFREQ] Disable sysfs ui for p4-clockmod."

[safe/jmp/linux-2.6] / arch / arm / mach-omap1 / irq.c

diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index a11b6d8..9ad5197 100644 (file)
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -1,11 +1,11 @@
 /*
- * linux/arch/arm/mach-omap/irq.c
+ * linux/arch/arm/mach-omap1/irq.c
  *
  * Interrupt handler for all OMAP boards
  *
  * Copyright (C) 2004 Nokia Corporation
  * Written by Tony Lindgren <tony@atomide.com>
- * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com>
+ * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com>
  *
  * Completely re-written to support various OMAP chips with bank specific
  * interrupt handlers.
@@ -36,19 +36,17 @@
  * 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#include <linux/config.h>
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/sched.h>
 #include <linux/interrupt.h>
-#include <linux/ptrace.h>
+#include <linux/io.h>
 
-#include <asm/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
-#include <asm/arch/gpio.h>
-
-#include <asm/io.h>
+#include <mach/gpio.h>
+#include <mach/cpu.h>
 
 #define IRQ_BANK(irq) ((irq) >> 5)
 #define IRQ_BIT(irq)  ((irq) & 0x1f)
@@ -59,7 +57,7 @@ struct omap_irq_bank {
        unsigned long wake_enable;
 };
 
-static unsigned int irq_bank_count = 0;
+static unsigned int irq_bank_count;
 static struct omap_irq_bank *irq_banks;
 
 static inline unsigned int irq_bank_readl(int bank, int offset)
@@ -141,34 +139,39 @@ static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
 
 #ifdef CONFIG_ARCH_OMAP730
 static struct omap_irq_bank omap730_irq_banks[] = {
-       { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3f8e22f },
-       { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xfdb9c1f2 },
+       { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3f8e22f },
+       { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xfdb9c1f2 },
        { .base_reg = OMAP_IH2_BASE + 0x100,    .trigger_map = 0x800040f3 },
 };
 #endif
 
-#ifdef CONFIG_ARCH_OMAP1510
+#ifdef CONFIG_ARCH_OMAP15XX
 static struct omap_irq_bank omap1510_irq_banks[] = {
-       { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3febfff },
-       { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xffbfffed },
+       { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3febfff },
+       { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xffbfffed },
+};
+static struct omap_irq_bank omap310_irq_banks[] = {
+       { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3faefc3 },
+       { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0x65b3c061 },
 };
 #endif
 
 #if defined(CONFIG_ARCH_OMAP16XX)
 
 static struct omap_irq_bank omap1610_irq_banks[] = {
-       { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3fefe8f },
-       { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xfdb7c1fd },
+       { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3fefe8f },
+       { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xfdb7c1fd },
        { .base_reg = OMAP_IH2_BASE + 0x100,    .trigger_map = 0xffffb7ff },
        { .base_reg = OMAP_IH2_BASE + 0x200,    .trigger_map = 0xffffffff },
 };
 #endif
 
-static struct irqchip omap_irq_chip = {
-       .ack    = omap_mask_ack_irq,
-       .mask   = omap_mask_irq,
-       .unmask = omap_unmask_irq,
-       .wake   = omap_wake_irq,
+static struct irq_chip omap_irq_chip = {
+       .name           = "MPU",
+       .ack            = omap_mask_ack_irq,
+       .mask           = omap_mask_irq,
+       .unmask         = omap_unmask_irq,
+       .set_wake       = omap_wake_irq,
 };
 
 void __init omap_init_irq(void)
@@ -181,11 +184,15 @@ void __init omap_init_irq(void)
                irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
        }
 #endif
-#ifdef CONFIG_ARCH_OMAP1510
+#ifdef CONFIG_ARCH_OMAP15XX
        if (cpu_is_omap1510()) {
                irq_banks = omap1510_irq_banks;
                irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
        }
+       if (cpu_is_omap310()) {
+               irq_banks = omap310_irq_banks;
+               irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
+       }
 #endif
 #if defined(CONFIG_ARCH_OMAP16XX)
        if (cpu_is_omap16xx()) {
@@ -220,15 +227,17 @@ void __init omap_init_irq(void)
                        omap_irq_set_cfg(j, 0, 0, irq_trigger);
 
                        set_irq_chip(j, &omap_irq_chip);
-                       set_irq_handler(j, do_level_IRQ);
+                       set_irq_handler(j, handle_level_irq);
                        set_irq_flags(j, IRQF_VALID);
                }
        }
 
        /* Unmask level 2 handler */
-       if (cpu_is_omap730()) {
+
+       if (cpu_is_omap730())
                omap_unmask_irq(INT_730_IH2_IRQ);
-       } else {
-               omap_unmask_irq(INT_IH2_IRQ);
-       }
+       else if (cpu_is_omap15xx())
+               omap_unmask_irq(INT_1510_IH2_IRQ);
+       else if (cpu_is_omap16xx())
+               omap_unmask_irq(INT_1610_IH2_IRQ);
 }