#include <linux/fs.h>
#include <asm/cpu.h>
+#include <asm/cputype.h>
#include <asm/elf.h>
#include <asm/procinfo.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/cacheflush.h>
+#include <asm/cachetype.h>
#include <asm/tlbflush.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
+#include <asm/traps.h>
#include "compat.h"
+#include "atags.h"
#ifndef MEM_SIZE
#define MEM_SIZE (16*1024*1024)
extern void _stext, _text, _etext, __data_start, _edata, _end;
unsigned int processor_id;
+EXPORT_SYMBOL(processor_id);
unsigned int __machine_arch_type;
EXPORT_SYMBOL(__machine_arch_type);
unsigned int elf_hwcap;
EXPORT_SYMBOL(elf_hwcap);
+unsigned long __initdata vmalloc_reserve = 128 << 20;
+
#ifdef MULTI_CPU
struct processor processor;
static void __init dump_cpu_info(int cpu)
{
- unsigned int info = read_cpuid(CPUID_CACHETYPE);
+ unsigned int info = read_cpuid_cachetype();
- if (info != processor_id) {
+ if (info != read_cpuid_id()) {
printk("CPU%u: D %s %s cache\n", cpu, cache_is_vivt() ? "VIVT" : "VIPT",
cache_types[CACHE_TYPE(info)]);
if (CACHE_S(info)) {
{
int cpu_arch;
- if ((processor_id & 0x0008f000) == 0) {
+ if ((read_cpuid_id() & 0x0008f000) == 0) {
cpu_arch = CPU_ARCH_UNKNOWN;
- } else if ((processor_id & 0x0008f000) == 0x00007000) {
- cpu_arch = (processor_id & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
- } else if ((processor_id & 0x00080000) == 0x00000000) {
- cpu_arch = (processor_id >> 16) & 7;
+ } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
+ cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
+ } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
+ cpu_arch = (read_cpuid_id() >> 16) & 7;
if (cpu_arch)
cpu_arch += CPU_ARCH_ARMv3;
- } else {
- /* the revised CPUID */
- cpu_arch = ((processor_id >> 12) & 0xf) - 0xb + CPU_ARCH_ARMv6;
- }
+ } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
+ unsigned int mmfr0;
+
+ /* Revised CPUID format. Read the Memory Model Feature
+ * Register 0 and check for VMSAv7 or PMSAv7 */
+ asm("mrc p15, 0, %0, c0, c1, 4"
+ : "=r" (mmfr0));
+ if ((mmfr0 & 0x0000000f) == 0x00000003 ||
+ (mmfr0 & 0x000000f0) == 0x00000030)
+ cpu_arch = CPU_ARCH_ARMv7;
+ else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
+ (mmfr0 & 0x000000f0) == 0x00000020)
+ cpu_arch = CPU_ARCH_ARMv6;
+ else
+ cpu_arch = CPU_ARCH_UNKNOWN;
+ } else
+ cpu_arch = CPU_ARCH_UNKNOWN;
return cpu_arch;
}
* types. The linker builds this table for us from the
* entries in arch/arm/mm/proc-*.S
*/
- list = lookup_processor_type(processor_id);
+ list = lookup_processor_type(read_cpuid_id());
if (!list) {
printk("CPU configuration botched (ID %08x), unable "
- "to continue.\n", processor_id);
+ "to continue.\n", read_cpuid_id());
while (1);
}
#endif
printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
- cpu_name, processor_id, (int)processor_id & 15,
+ cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
proc_arch[cpu_architecture()], cr_alignment);
sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS);
__early_param("mem=", early_mem);
/*
+ * vmalloc=size forces the vmalloc area to be exactly 'size'
+ * bytes. This can be used to increase (or decrease) the vmalloc
+ * area - the default is 128m.
+ */
+static void __init early_vmalloc(char **arg)
+{
+ vmalloc_reserve = memparse(*arg, arg);
+}
+__early_param("vmalloc=", early_vmalloc);
+
+/*
* Initial parsing of the command line.
*/
static void __init parse_cmdline(char **cmdline_p, char *from)
if (tags->hdr.tag == ATAG_CORE) {
if (meminfo.nr_banks != 0)
squash_mem_tags(tags);
+ save_atags(tags);
parse_tags(tags);
}
conswitchp = &dummy_con;
#endif
#endif
+ early_trap_init();
}
int i;
seq_printf(m, "Processor\t: %s rev %d (%s)\n",
- cpu_name, (int)processor_id & 15, elf_platform);
+ cpu_name, read_cpuid_id() & 15, elf_platform);
#if defined(CONFIG_SMP)
for_each_online_cpu(i) {
if (elf_hwcap & (1 << i))
seq_printf(m, "%s ", hwcap_str[i]);
- seq_printf(m, "\nCPU implementer\t: 0x%02x\n", processor_id >> 24);
+ seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
seq_printf(m, "CPU architecture: %s\n", proc_arch[cpu_architecture()]);
- if ((processor_id & 0x0008f000) == 0x00000000) {
+ if ((read_cpuid_id() & 0x0008f000) == 0x00000000) {
/* pre-ARM7 */
- seq_printf(m, "CPU part\t: %07x\n", processor_id >> 4);
+ seq_printf(m, "CPU part\t: %07x\n", read_cpuid_id() >> 4);
} else {
- if ((processor_id & 0x0008f000) == 0x00007000) {
+ if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
/* ARM7 */
seq_printf(m, "CPU variant\t: 0x%02x\n",
- (processor_id >> 16) & 127);
+ (read_cpuid_id() >> 16) & 127);
} else {
/* post-ARM7 */
seq_printf(m, "CPU variant\t: 0x%x\n",
- (processor_id >> 20) & 15);
+ (read_cpuid_id() >> 20) & 15);
}
seq_printf(m, "CPU part\t: 0x%03x\n",
- (processor_id >> 4) & 0xfff);
+ (read_cpuid_id() >> 4) & 0xfff);
}
- seq_printf(m, "CPU revision\t: %d\n", processor_id & 15);
+ seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
{
- unsigned int cache_info = read_cpuid(CPUID_CACHETYPE);
- if (cache_info != processor_id) {
+ unsigned int cache_info = read_cpuid_cachetype();
+ if (cache_info != read_cpuid_id()) {
seq_printf(m, "Cache type\t: %s\n"
"Cache clean\t: %s\n"
"Cache lockdown\t: %s\n"
{
}
-struct seq_operations cpuinfo_op = {
+const struct seq_operations cpuinfo_op = {
.start = c_start,
.next = c_next,
.stop = c_stop,
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff