[ARM] cachetype: move definitions to separate header

[safe/jmp/linux-2.6] / arch / arm / kernel / setup.c

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 2ca7038..e90422d 100644 (file)
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -26,11 +26,13 @@
 #include <linux/fs.h>
 
 #include <asm/cpu.h>
+#include <asm/cputype.h>
 #include <asm/elf.h>
 #include <asm/procinfo.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/cacheflush.h>
+#include <asm/cachetype.h>
 #include <asm/tlbflush.h>
 
 #include <asm/mach/arch.h>
@@ -280,9 +282,9 @@ static inline void dump_cache(const char *prefix, int cpu, unsigned int cache)
 
 static void __init dump_cpu_info(int cpu)
 {
-       unsigned int info = read_cpuid(CPUID_CACHETYPE);
+       unsigned int info = read_cpuid_cachetype();
 
-       if (info != processor_id) {
+       if (info != read_cpuid_id()) {
                printk("CPU%u: D %s %s cache\n", cpu, cache_is_vivt() ? "VIVT" : "VIPT",
                       cache_types[CACHE_TYPE(info)]);
                if (CACHE_S(info)) {
@@ -301,15 +303,15 @@ int cpu_architecture(void)
 {
        int cpu_arch;
 
-       if ((processor_id & 0x0008f000) == 0) {
+       if ((read_cpuid_id() & 0x0008f000) == 0) {
                cpu_arch = CPU_ARCH_UNKNOWN;
-       } else if ((processor_id & 0x0008f000) == 0x00007000) {
-               cpu_arch = (processor_id & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
-       } else if ((processor_id & 0x00080000) == 0x00000000) {
-               cpu_arch = (processor_id >> 16) & 7;
+       } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
+               cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
+       } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
+               cpu_arch = (read_cpuid_id() >> 16) & 7;
                if (cpu_arch)
                        cpu_arch += CPU_ARCH_ARMv3;
-       } else if ((processor_id & 0x000f0000) == 0x000f0000) {
+       } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
                unsigned int mmfr0;
 
                /* Revised CPUID format. Read the Memory Model Feature
@@ -346,10 +348,10 @@ static void __init setup_processor(void)
         * types.  The linker builds this table for us from the
         * entries in arch/arm/mm/proc-*.S
         */
-       list = lookup_processor_type(processor_id);
+       list = lookup_processor_type(read_cpuid_id());
        if (!list) {
                printk("CPU configuration botched (ID %08x), unable "
-                      "to continue.\n", processor_id);
+                      "to continue.\n", read_cpuid_id());
                while (1);
        }
 
@@ -369,7 +371,7 @@ static void __init setup_processor(void)
 #endif
 
        printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
-              cpu_name, processor_id, (int)processor_id & 15,
+              cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
               proc_arch[cpu_architecture()], cr_alignment);
 
        sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS);
@@ -922,7 +924,7 @@ static int c_show(struct seq_file *m, void *v)
        int i;
 
        seq_printf(m, "Processor\t: %s rev %d (%s)\n",
-                  cpu_name, (int)processor_id & 15, elf_platform);
+                  cpu_name, read_cpuid_id() & 15, elf_platform);
 
 #if defined(CONFIG_SMP)
        for_each_online_cpu(i) {
@@ -949,30 +951,30 @@ static int c_show(struct seq_file *m, void *v)
                if (elf_hwcap & (1 << i))
                        seq_printf(m, "%s ", hwcap_str[i]);
 
-       seq_printf(m, "\nCPU implementer\t: 0x%02x\n", processor_id >> 24);
+       seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
        seq_printf(m, "CPU architecture: %s\n", proc_arch[cpu_architecture()]);
 
-       if ((processor_id & 0x0008f000) == 0x00000000) {
+       if ((read_cpuid_id() & 0x0008f000) == 0x00000000) {
                /* pre-ARM7 */
-               seq_printf(m, "CPU part\t: %07x\n", processor_id >> 4);
+               seq_printf(m, "CPU part\t: %07x\n", read_cpuid_id() >> 4);
        } else {
-               if ((processor_id & 0x0008f000) == 0x00007000) {
+               if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
                        /* ARM7 */
                        seq_printf(m, "CPU variant\t: 0x%02x\n",
-                                  (processor_id >> 16) & 127);
+                                  (read_cpuid_id() >> 16) & 127);
                } else {
                        /* post-ARM7 */
                        seq_printf(m, "CPU variant\t: 0x%x\n",
-                                  (processor_id >> 20) & 15);
+                                  (read_cpuid_id() >> 20) & 15);
                }
                seq_printf(m, "CPU part\t: 0x%03x\n",
-                          (processor_id >> 4) & 0xfff);
+                          (read_cpuid_id() >> 4) & 0xfff);
        }
-       seq_printf(m, "CPU revision\t: %d\n", processor_id & 15);
+       seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
 
        {
-               unsigned int cache_info = read_cpuid(CPUID_CACHETYPE);
-               if (cache_info != processor_id) {
+               unsigned int cache_info = read_cpuid_cachetype();
+               if (cache_info != read_cpuid_id()) {
                        seq_printf(m, "Cache type\t: %s\n"
                                      "Cache clean\t: %s\n"
                                      "Cache lockdown\t: %s\n"