-#define ACPI_FADT_COMMON \
- ACPI_TABLE_HEADER_DEF \
- u32 V1_firmware_ctrl; /* 32-bit physical address of FACS */ \
- u32 V1_dsdt; /* 32-bit physical address of DSDT */ \
- u8 reserved1; /* System Interrupt Model isn't used in ACPI 2.0*/ \
- u8 prefer_PM_profile; /* Conveys preferred power management profile to OSPM. */ \
- u16 sci_int; /* System vector of SCI interrupt */ \
- u32 smi_cmd; /* Port address of SMI command port */ \
- u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */ \
- u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */ \
- u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */ \
- u8 pstate_cnt; /* Processor performance state control*/ \
- u32 V1_pm1a_evt_blk; /* Port address of Power Mgt 1a Event Reg Blk */ \
- u32 V1_pm1b_evt_blk; /* Port address of Power Mgt 1b Event Reg Blk */ \
- u32 V1_pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */ \
- u32 V1_pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */ \
- u32 V1_pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */ \
- u32 V1_pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ \
- u32 V1_gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */ \
- u32 V1_gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */ \
- u8 pm1_evt_len; /* Byte Length of ports at pm1_x_evt_blk */ \
- u8 pm1_cnt_len; /* Byte Length of ports at pm1_x_cnt_blk */ \
- u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */ \
- u8 pm_tm_len; /* Byte Length of ports at pm_tm_blk */ \
- u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */ \
- u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */ \
- u8 gpe1_base; /* Offset in gpe model where gpe1 events start */ \
- u8 cst_cnt; /* Support for the _CST object and C States change notification.*/ \
- u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */ \
- u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */ \
- u16 flush_size; /* Processor's memory cache line width, in bytes */ \
- u16 flush_stride; /* Number of flush strides that need to be read */ \
- u8 duty_offset; /* Processor's duty cycle index in processor's P_CNT reg*/ \
- u8 duty_width; /* Processor's duty cycle value bit width in P_CNT register.*/ \
- u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */ \
- u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */ \
- u8 century; /* Index to century in RTC CMOS RAM */ \
- u16 iapc_boot_arch; /* IA-PC Boot Architecture Flags. See Table 5-10 for description*/ \
- u8 reserved2; /* Reserved, must be zero */
-
-/*
- * ACPI 2.0+ FADT
- */
-struct fadt_descriptor {
- ACPI_FADT_COMMON
- /* Flags (32 bits) */
- u8 wb_invd:1; /* 00: The wbinvd instruction works properly */
- u8 wb_invd_flush:1; /* 01: The wbinvd flushes but does not invalidate */
- u8 proc_c1:1; /* 02: All processors support C1 state */
- u8 plvl2_up:1; /* 03: C2 state works on MP system */
- u8 pwr_button:1; /* 04: Power button is handled as a generic feature */
- u8 sleep_button:1; /* 05: Sleep button is handled as a generic feature, or not present */
- u8 fixed_rTC:1; /* 06: RTC wakeup stat not in fixed register space */
- u8 rtcs4:1; /* 07: RTC wakeup stat not possible from S4 */
- u8 tmr_val_ext:1; /* 08: tmr_val is 32 bits 0=24-bits */
- u8 dock_cap:1; /* 09: Docking supported */
- u8 reset_reg_sup:1; /* 10: System reset via the FADT RESET_REG supported */
- u8 sealed_case:1; /* 11: No internal expansion capabilities and case is sealed */
- u8 headless:1; /* 12: No local video capabilities or local input devices */
- u8 cpu_sw_sleep:1; /* 13: Must execute native instruction after writing SLP_TYPx register */
-
- u8 pci_exp_wak:1; /* 14: System supports PCIEXP_WAKE (STS/EN) bits (ACPI 3.0) */
- u8 use_platform_clock:1; /* 15: OSPM should use platform-provided timer (ACPI 3.0) */
- u8 S4rtc_sts_valid:1; /* 16: Contents of RTC_STS valid after S4 wake (ACPI 3.0) */
- u8 remote_power_on_capable:1; /* 17: System is compatible with remote power on (ACPI 3.0) */
- u8 force_apic_cluster_model:1; /* 18: All local APICs must use cluster model (ACPI 3.0) */
- u8 force_apic_physical_destination_mode:1; /* 19: All local x_aPICs must use physical dest mode (ACPI 3.0) */
- u8:4; /* 20-23: Reserved, must be zero */
- u8 reserved3; /* 24-31: Reserved, must be zero */
-
- struct acpi_generic_address reset_register; /* Reset register address in GAS format */
+struct acpi_table_fadt {
+ struct acpi_table_header header; /* Common ACPI table header */
+ u32 facs; /* 32-bit physical address of FACS */
+ u32 dsdt; /* 32-bit physical address of DSDT */
+ u8 model; /* System Interrupt Model (ACPI 1.0) - not used in ACPI 2.0+ */
+ u8 preferred_profile; /* Conveys preferred power management profile to OSPM. */
+ u16 sci_interrupt; /* System vector of SCI interrupt */
+ u32 smi_command; /* 32-bit Port address of SMI command port */
+ u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
+ u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
+ u8 S4bios_request; /* Value to write to SMI CMD to enter S4BIOS state */
+ u8 pstate_control; /* Processor performance state control */
+ u32 pm1a_event_block; /* 32-bit Port address of Power Mgt 1a Event Reg Blk */
+ u32 pm1b_event_block; /* 32-bit Port address of Power Mgt 1b Event Reg Blk */
+ u32 pm1a_control_block; /* 32-bit Port address of Power Mgt 1a Control Reg Blk */
+ u32 pm1b_control_block; /* 32-bit Port address of Power Mgt 1b Control Reg Blk */
+ u32 pm2_control_block; /* 32-bit Port address of Power Mgt 2 Control Reg Blk */
+ u32 pm_timer_block; /* 32-bit Port address of Power Mgt Timer Ctrl Reg Blk */
+ u32 gpe0_block; /* 32-bit Port address of General Purpose Event 0 Reg Blk */
+ u32 gpe1_block; /* 32-bit Port address of General Purpose Event 1 Reg Blk */
+ u8 pm1_event_length; /* Byte Length of ports at pm1x_event_block */
+ u8 pm1_control_length; /* Byte Length of ports at pm1x_control_block */
+ u8 pm2_control_length; /* Byte Length of ports at pm2_control_block */
+ u8 pm_timer_length; /* Byte Length of ports at pm_timer_block */
+ u8 gpe0_block_length; /* Byte Length of ports at gpe0_block */
+ u8 gpe1_block_length; /* Byte Length of ports at gpe1_block */
+ u8 gpe1_base; /* Offset in GPE number space where GPE1 events start */
+ u8 cst_control; /* Support for the _CST object and C States change notification */
+ u16 C2latency; /* Worst case HW latency to enter/exit C2 state */
+ u16 C3latency; /* Worst case HW latency to enter/exit C3 state */
+ u16 flush_size; /* Processor's memory cache line width, in bytes */
+ u16 flush_stride; /* Number of flush strides that need to be read */
+ u8 duty_offset; /* Processor duty cycle index in processor's P_CNT reg */
+ u8 duty_width; /* Processor duty cycle value bit width in P_CNT register */
+ u8 day_alarm; /* Index to day-of-month alarm in RTC CMOS RAM */
+ u8 month_alarm; /* Index to month-of-year alarm in RTC CMOS RAM */
+ u8 century; /* Index to century in RTC CMOS RAM */
+ u16 boot_flags; /* IA-PC Boot Architecture Flags (see below for individual flags) */
+ u8 reserved; /* Reserved, must be zero */
+ u32 flags; /* Miscellaneous flag bits (see below for individual flags) */
+ struct acpi_generic_address reset_register; /* 64-bit address of the Reset register */