[IA64] Don't go beyond iosapic_intr_info's arraysize

[safe/jmp/linux-2.6] / drivers / dma / Kconfig

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 6239c3d..48ea59e 100644 (file)
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -4,13 +4,14 @@
 
 menuconfig DMADEVICES
        bool "DMA Engine support"
 
 menuconfig DMADEVICES
        bool "DMA Engine support"

-       depends on (PCI && X86) || ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX || PPC
-       depends on !HIGHMEM64G
+       depends on !HIGHMEM64G && HAS_DMA

        help
          DMA engines can do asynchronous data transfers without
          involving the host CPU.  Currently, this framework can be
          used to offload memory copies in the network stack and
        help
          DMA engines can do asynchronous data transfers without
          involving the host CPU.  Currently, this framework can be
          used to offload memory copies in the network stack and

-         RAID operations in the MD driver.
+         RAID operations in the MD driver.  This menu only presents
+         DMA Device drivers supported by the configured arch, it may
+         be empty in some cases.

 
 if DMADEVICES
 
 
 if DMADEVICES
 


@@ -32,19 +33,53 @@ config INTEL_IOATDMA
 config INTEL_IOP_ADMA
        tristate "Intel IOP ADMA support"
        depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
 config INTEL_IOP_ADMA
        tristate "Intel IOP ADMA support"
        depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX

-       select ASYNC_CORE

        select DMA_ENGINE
        help
          Enable support for the Intel(R) IOP Series RAID engines.
 
        select DMA_ENGINE
        help
          Enable support for the Intel(R) IOP Series RAID engines.
 

+config DW_DMAC
+       tristate "Synopsys DesignWare AHB DMA support"
+       depends on AVR32
+       select DMA_ENGINE
+       default y if CPU_AT32AP7000
+       help
+         Support the Synopsys DesignWare AHB DMA controller.  This
+         can be integrated in chips such as the Atmel AT32ap7000.
+

 config FSL_DMA
 config FSL_DMA

-       bool "Freescale MPC85xx/MPC83xx DMA support"
-       depends on PPC
+       tristate "Freescale Elo and Elo Plus DMA support"
+       depends on FSL_SOC
+       select DMA_ENGINE
+       ---help---
+         Enable support for the Freescale Elo and Elo Plus DMA controllers.
+         The Elo is the DMA controller on some 82xx and 83xx parts, and the
+         Elo Plus is the DMA controller on 85xx and 86xx parts.
+
+config MV_XOR
+       bool "Marvell XOR engine support"
+       depends on PLAT_ORION

        select DMA_ENGINE
        ---help---
        select DMA_ENGINE
        ---help---

-         Enable support for the Freescale DMA engine. Now, it support
-         MPC8560/40, MPC8555, MPC8548 and MPC8641 processors.
-         The MPC8349, MPC8360 is also supported.
+         Enable support for the Marvell XOR engine.
+
+config MX3_IPU
+       bool "MX3x Image Processing Unit support"
+       depends on ARCH_MX3
+       select DMA_ENGINE
+       default y
+       help
+         If you plan to use the Image Processing unit in the i.MX3x, say
+         Y here. If unsure, select Y.
+
+config MX3_IPU_IRQS
+       int "Number of dynamically mapped interrupts for IPU"
+       depends on MX3_IPU
+       range 2 137
+       default 4
+       help
+         Out of 137 interrupt sources on i.MX31 IPU only very few are used.
+         To avoid bloating the irq_desc[] array we allocate a sufficient
+         number of IRQ slots and map them dynamically to specific sources.

 
 config DMA_ENGINE
        bool
 
 config DMA_ENGINE
        bool


@@ -55,10 +90,19 @@ comment "DMA Clients"
 config NET_DMA
        bool "Network: TCP receive copy offload"
        depends on DMA_ENGINE && NET
 config NET_DMA
        bool "Network: TCP receive copy offload"
        depends on DMA_ENGINE && NET

+       default (INTEL_IOATDMA || FSL_DMA)

        help
          This enables the use of DMA engines in the network stack to
          offload receive copy-to-user operations, freeing CPU cycles.
        help
          This enables the use of DMA engines in the network stack to
          offload receive copy-to-user operations, freeing CPU cycles.

-         Since this is the main user of the DMA engine, it should be enabled;
-         say Y here.
+
+         Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
+         say N.
+
+config DMATEST
+       tristate "DMA Test client"
+       depends on DMA_ENGINE
+       help
+         Simple DMA test client. Say N unless you're debugging a
+         DMA Device driver.

 
 endif
 
 endif