Blackfin: decouple unrelated cache settings to get exact behavior

[safe/jmp/linux-2.6] / arch / blackfin / Kconfig

diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index be54e36..220635a 100644 (file)
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -6,62 +6,65 @@
 mainmenu "Blackfin Kernel Configuration"
 
 config MMU
 mainmenu "Blackfin Kernel Configuration"
 
 config MMU

-       bool
-       default n
+       def_bool n

 
 config FPU
 
 config FPU

-       bool
-       default n
+       def_bool n

 
 config RWSEM_GENERIC_SPINLOCK
 
 config RWSEM_GENERIC_SPINLOCK

-       bool
-       default y
+       def_bool y

 
 config RWSEM_XCHGADD_ALGORITHM
 
 config RWSEM_XCHGADD_ALGORITHM

-       bool
-       default n
+       def_bool n

 
 config BLACKFIN
 
 config BLACKFIN

-       bool
-       default y
+       def_bool y
+       select HAVE_FUNCTION_GRAPH_TRACER
+       select HAVE_FUNCTION_TRACER

        select HAVE_IDE
        select HAVE_IDE

+       select HAVE_KERNEL_GZIP
+       select HAVE_KERNEL_BZIP2
+       select HAVE_KERNEL_LZMA

        select HAVE_OPROFILE
        select HAVE_OPROFILE

+       select ARCH_WANT_OPTIONAL_GPIOLIB
+
+config GENERIC_BUG
+       def_bool y
+       depends on BUG

 
 config ZONE_DMA
 
 config ZONE_DMA

-       bool
-       default y
+       def_bool y

 
 config GENERIC_FIND_NEXT_BIT
 
 config GENERIC_FIND_NEXT_BIT

-       bool
-       default y
+       def_bool y

 
 config GENERIC_HWEIGHT
 
 config GENERIC_HWEIGHT

-       bool
-       default y
+       def_bool y

 
 config GENERIC_HARDIRQS
 
 config GENERIC_HARDIRQS

-       bool
-       default y
+       def_bool y

 
 config GENERIC_IRQ_PROBE
 
 config GENERIC_IRQ_PROBE

-       bool
-       default y
+       def_bool y

 
 config GENERIC_GPIO
 
 config GENERIC_GPIO

-       bool
-       default y
+       def_bool y

 
 config FORCE_MAX_ZONEORDER
        int
        default "14"
 
 config GENERIC_CALIBRATE_DELAY
 
 config FORCE_MAX_ZONEORDER
        int
        default "14"
 
 config GENERIC_CALIBRATE_DELAY

-       bool
-       default y
+       def_bool y
+
+config LOCKDEP_SUPPORT
+       def_bool y
+
+config STACKTRACE_SUPPORT
+       def_bool y

 
 

-config HARDWARE_PM
+config TRACE_IRQFLAGS_SUPPORT

        def_bool y
        def_bool y

-       depends on OPROFILE

 
 source "init/Kconfig"
 
 
 source "init/Kconfig"
 


@@ -77,6 +80,26 @@ choice
        prompt "CPU"
        default BF533
 
        prompt "CPU"
        default BF533
 

+config BF512
+       bool "BF512"
+       help
+         BF512 Processor Support.
+
+config BF514
+       bool "BF514"
+       help
+         BF514 Processor Support.
+
+config BF516
+       bool "BF516"
+       help
+         BF516 Processor Support.
+
+config BF518
+       bool "BF518"
+       help
+         BF518 Processor Support.
+

 config BF522
        bool "BF522"
        help
 config BF522
        bool "BF522"
        help


@@ -152,26 +175,51 @@ config BF542
        help
          BF542 Processor Support.
 
        help
          BF542 Processor Support.
 

+config BF542M
+       bool "BF542m"
+       help
+         BF542 Processor Support.
+

 config BF544
        bool "BF544"
        help
          BF544 Processor Support.
 
 config BF544
        bool "BF544"
        help
          BF544 Processor Support.
 

+config BF544M
+       bool "BF544m"
+       help
+         BF544 Processor Support.
+

 config BF547
        bool "BF547"
        help
          BF547 Processor Support.
 
 config BF547
        bool "BF547"
        help
          BF547 Processor Support.
 

+config BF547M
+       bool "BF547m"
+       help
+         BF547 Processor Support.
+

 config BF548
        bool "BF548"
        help
          BF548 Processor Support.
 
 config BF548
        bool "BF548"
        help
          BF548 Processor Support.
 

+config BF548M
+       bool "BF548m"
+       help
+         BF548 Processor Support.
+

 config BF549
        bool "BF549"
        help
          BF549 Processor Support.
 
 config BF549
        bool "BF549"
        help
          BF549 Processor Support.
 

+config BF549M
+       bool "BF549m"
+       help
+         BF549 Processor Support.
+

 config BF561
        bool "BF561"
        help
 config BF561
        bool "BF561"
        help


@@ -179,41 +227,62 @@ config BF561
 
 endchoice
 
 
 endchoice
 

+config SMP
+       depends on BF561
+       select GENERIC_TIME
+       bool "Symmetric multi-processing support"
+       ---help---
+         This enables support for systems with more than one CPU,
+         like the dual core BF561. If you have a system with only one
+         CPU, say N. If you have a system with more than one CPU, say Y.
+
+         If you don't know what to do here, say N.
+
+config NR_CPUS
+       int
+       depends on SMP
+       default 2 if BF561
+
+config IRQ_PER_CPU
+       bool
+       depends on SMP
+       default y
+

 config BF_REV_MIN
        int
 config BF_REV_MIN
        int

-       default 0 if (BF52x || BF54x)
+       default 0 if (BF51x || BF52x || (BF54x && !BF54xM))

        default 2 if (BF537 || BF536 || BF534)
        default 2 if (BF537 || BF536 || BF534)

-       default 3 if (BF561 ||BF533 || BF532 || BF531)
-       default 4 if (BF538 || BF539)   
+       default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
+       default 4 if (BF538 || BF539)

 
 config BF_REV_MAX
        int
 
 config BF_REV_MAX
        int

-       default 2 if (BF52x || BF54x)
-       default 3 if (BF537 || BF536 || BF534)
-       default 5 if (BF561|| BF538 || BF539)
+       default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
+       default 3 if (BF537 || BF536 || BF534 || BF54xM)
+       default 5 if (BF561 || BF538 || BF539)

        default 6 if (BF533 || BF532 || BF531)
 
 choice
        prompt "Silicon Rev"
        default 6 if (BF533 || BF532 || BF531)
 
 choice
        prompt "Silicon Rev"

-       default BF_REV_0_1 if (BF52x || BF54x)
-       default BF_REV_0_2 if (BF534 || BF536 || BF537)
-       default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
+       default BF_REV_0_0 if (BF51x || BF52x)
+       default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
+       default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)

 
 config BF_REV_0_0
        bool "0.0"
 
 config BF_REV_0_0
        bool "0.0"

-       depends on (BF52x || BF54x)
+       depends on (BF51x || BF52x || (BF54x && !BF54xM))

 
 config BF_REV_0_1
        bool "0.1"
 
 config BF_REV_0_1
        bool "0.1"

-       depends on (BF52x || BF54x)
+       depends on (BF51x || BF52x || (BF54x && !BF54xM))

 
 config BF_REV_0_2
        bool "0.2"
 
 config BF_REV_0_2
        bool "0.2"

-       depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
+       depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))

 
 config BF_REV_0_3
        bool "0.3"
 
 config BF_REV_0_3
        bool "0.3"

-       depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
+       depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)

 
 config BF_REV_0_4
        bool "0.4"
 
 config BF_REV_0_4
        bool "0.4"


@@ -235,6 +304,11 @@ config BF_REV_NONE
 
 endchoice
 
 
 endchoice
 

+config BF51x
+       bool
+       depends on (BF512 || BF514 || BF516 || BF518)
+       default y
+

 config BF52x
        bool
        depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
 config BF52x
        bool
        depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)


@@ -245,9 +319,14 @@ config BF53x
        depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
        default y
 
        depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
        default y
 

+config BF54xM
+       bool
+       depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
+       default y
+

 config BF54x
        bool
 config BF54x
        bool

-       depends on (BF542 || BF544 || BF547 || BF548 || BF549)
+       depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)

        default y
 
 config MEM_GENERIC_BOARD
        default y
 
 config MEM_GENERIC_BOARD


@@ -282,6 +361,12 @@ config MEM_MT48LC32M16A2TG_75
        depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
        default y
 
        depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
        default y
 

+config MEM_MT48LC32M8A2_75
+       bool
+       depends on (BFIN518F_EZBRD)
+       default y
+
+source "arch/blackfin/mach-bf518/Kconfig"

 source "arch/blackfin/mach-bf527/Kconfig"
 source "arch/blackfin/mach-bf533/Kconfig"
 source "arch/blackfin/mach-bf561/Kconfig"
 source "arch/blackfin/mach-bf527/Kconfig"
 source "arch/blackfin/mach-bf533/Kconfig"
 source "arch/blackfin/mach-bf561/Kconfig"


@@ -319,6 +404,7 @@ config BOOT_LOAD
 
 config ROM_BASE
        hex "Kernel ROM Base"
 
 config ROM_BASE
        hex "Kernel ROM Base"

+       depends on ROMKERNEL

        default "0x20040000"
        range 0x20000000 0x20400000 if !(BF54x || BF561)
        range 0x20000000 0x30000000 if (BF54x || BF561)
        default "0x20040000"
        range 0x20000000 0x20400000 if !(BF54x || BF561)
        range 0x20000000 0x30000000 if (BF54x || BF561)


@@ -328,12 +414,12 @@ comment "Clock/PLL Setup"
 
 config CLKIN_HZ
        int "Frequency of the crystal on the board in Hz"
 
 config CLKIN_HZ
        int "Frequency of the crystal on the board in Hz"

+       default "10000000" if BFIN532_IP0X

        default "11059200" if BFIN533_STAMP
        default "11059200" if BFIN533_STAMP

+       default "24576000" if PNAV10
+       default "25000000" # most people use this

        default "27000000" if BFIN533_EZKIT
        default "27000000" if BFIN533_EZKIT

-       default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT)

        default "30000000" if BFIN561_EZKIT
        default "30000000" if BFIN561_EZKIT

-       default "24576000" if PNAV10
-       default "10000000" if BFIN532_IP0X

        help
          The frequency of CLKIN crystal oscillator on the board in Hz.
          Warning: This value should match the crystal on the board. Otherwise,
        help
          The frequency of CLKIN crystal oscillator on the board in Hz.
          Warning: This value should match the crystal on the board. Otherwise,


@@ -370,7 +456,7 @@ config VCO_MULT
        default "22" if BFIN533_BLUETECHNIX_CM
        default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
        default "20" if BFIN561_EZKIT
        default "22" if BFIN533_BLUETECHNIX_CM
        default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
        default "20" if BFIN561_EZKIT

-       default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
+       default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)

        help
          This controls the frequency of the on-chip PLL. This can be between 1 and 64.
          PLL Frequency = (Crystal Frequency) * (this setting)
        help
          This controls the frequency of the on-chip PLL. This can be between 1 and 64.
          PLL Frequency = (Crystal Frequency) * (this setting)


@@ -419,19 +505,70 @@ config MEM_MT46V32M16_5B
        bool "MT46V32M16_5B"
 endchoice
 
        bool "MT46V32M16_5B"
 endchoice
 

-config MAX_MEM_SIZE
-       int "Max SDRAM Memory Size in MBytes"
-       depends on !MPU
-       default 512
+choice
+       prompt "DDR/SDRAM Timing"
+       depends on BFIN_KERNEL_CLOCK
+       default BFIN_KERNEL_CLOCK_MEMINIT_CALC
+       help
+         This option allows you to specify Blackfin SDRAM/DDR Timing parameters
+         The calculated SDRAM timing parameters may not be 100%
+         accurate - This option is therefore marked experimental.
+
+config BFIN_KERNEL_CLOCK_MEMINIT_CALC
+       bool "Calculate Timings (EXPERIMENTAL)"
+       depends on EXPERIMENTAL
+
+config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
+       bool "Provide accurate Timings based on target SCLK"

        help
        help

-         This is the max memory size that the kernel will create CPLB
-         tables for.  Your system will not be able to handle any more.
+         Please consult the Blackfin Hardware Reference Manuals as well
+         as the memory device datasheet.
+         http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
+endchoice
+
+menu "Memory Init Control"
+       depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
+
+config MEM_DDRCTL0
+       depends on BF54x
+       hex "DDRCTL0"
+       default 0x0
+
+config MEM_DDRCTL1
+       depends on BF54x
+       hex "DDRCTL1"
+       default 0x0
+
+config MEM_DDRCTL2
+       depends on BF54x
+       hex "DDRCTL2"
+       default 0x0
+
+config MEM_EBIU_DDRQUE
+       depends on BF54x
+       hex "DDRQUE"
+       default 0x0
+
+config MEM_SDRRC
+       depends on !BF54x
+       hex "SDRRC"
+       default 0x0
+
+config MEM_SDGCTL
+       depends on !BF54x
+       hex "SDGCTL"
+       default 0x0
+endmenu

 
 #
 # Max & Min Speeds for various Chips
 #
 config MAX_VCO_HZ
        int
 
 #
 # Max & Min Speeds for various Chips
 #
 config MAX_VCO_HZ
        int

+       default 400000000 if BF512
+       default 400000000 if BF514
+       default 400000000 if BF516
+       default 400000000 if BF518

        default 600000000 if BF522
        default 400000000 if BF523
        default 400000000 if BF524
        default 600000000 if BF522
        default 400000000 if BF523
        default 400000000 if BF524


@@ -478,12 +615,25 @@ config GENERIC_CLOCKEVENTS
        depends on GENERIC_TIME
        default y
 
        depends on GENERIC_TIME
        default y
 

+choice
+       prompt "Kernel Tick Source"
+       depends on GENERIC_CLOCKEVENTS
+       default TICKSOURCE_CORETMR
+
+config TICKSOURCE_GPTMR0
+       bool "Gptimer0 (SCLK domain)"
+       select BFIN_GPTIMERS
+
+config TICKSOURCE_CORETMR
+       bool "Core timer (CCLK domain)"
+
+endchoice
+

 config CYCLES_CLOCKSOURCE
 config CYCLES_CLOCKSOURCE

-       bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
-       depends on EXPERIMENTAL
+       bool "Use 'CYCLES' as a clocksource"

        depends on GENERIC_CLOCKEVENTS
        depends on !BFIN_SCRATCH_REG_CYCLES
        depends on GENERIC_CLOCKEVENTS
        depends on !BFIN_SCRATCH_REG_CYCLES

-       default n
+       depends on !SMP

        help
          If you say Y here, you will enable support for using the 'cycles'
          registers as a clock source.  Doing so means you will be unable to
        help
          If you say Y here, you will enable support for using the 'cycles'
          registers as a clock source.  Doing so means you will be unable to


@@ -491,6 +641,11 @@ config CYCLES_CLOCKSOURCE
          still be able to read it (such as for performance monitoring), but
          writing the registers will most likely crash the kernel.
 
          still be able to read it (such as for performance monitoring), but
          writing the registers will most likely crash the kernel.
 

+config GPTMR0_CLOCKSOURCE
+       bool "Use GPTimer0 as a clocksource (higher rating)"
+       depends on GENERIC_CLOCKEVENTS
+       depends on !TICKSOURCE_GPTMR0
+

 source kernel/time/Kconfig
 
 comment "Misc"
 source kernel/time/Kconfig
 
 comment "Misc"


@@ -545,6 +700,7 @@ endmenu
 
 
 menu "Blackfin Kernel Optimizations"
 
 
 menu "Blackfin Kernel Optimizations"

+       depends on !SMP

 
 comment "Memory Optimizations"
 
 
 comment "Memory Optimizations"
 


@@ -639,7 +795,7 @@ config CACHELINE_ALIGNED_L1
        default n if BF54x
        depends on !BF531
        help
        default n if BF54x
        depends on !BF531
        help

-         If enabled, cacheline_anligned data is linked
+         If enabled, cacheline_aligned data is linked

          into L1 data memory. (less latency)
 
 config SYSCALL_TAB_L1
          into L1 data memory. (less latency)
 
 config SYSCALL_TAB_L1


@@ -670,7 +826,7 @@ config APP_STACK_L1
 config EXCEPTION_L1_SCRATCH
        bool "Locate exception stack in L1 Scratch Memory"
        default n
 config EXCEPTION_L1_SCRATCH
        bool "Locate exception stack in L1 Scratch Memory"
        default n

-       depends on !APP_STACK_L1 && !SYSCALL_TAB_L1
+       depends on !APP_STACK_L1

        help
          Whenever an exception occurs, use the L1 Scratch memory for
          stack storage.  You cannot place the stacks of FLAT binaries
        help
          Whenever an exception occurs, use the L1 Scratch memory for
          stack storage.  You cannot place the stacks of FLAT binaries


@@ -707,7 +863,6 @@ config BFIN_INS_LOWOVERHEAD
 
 endmenu
 
 
 endmenu
 

-

 choice
        prompt "Kernel executes from"
        help
 choice
        prompt "Kernel executes from"
        help


@@ -735,18 +890,11 @@ config BFIN_GPTIMERS
          are unsure, say N.
 
          To compile this driver as a module, choose M here: the module
          are unsure, say N.
 
          To compile this driver as a module, choose M here: the module

-         will be called gptimers.ko.
-
-config BFIN_DMA_5XX
-       bool "Enable DMA Support"
-       default y
-       help
-         DMA driver for Blackfin parts.
+         will be called gptimers.

 
 choice
        prompt "Uncached DMA region"
        default DMA_UNCACHED_1M
 
 choice
        prompt "Uncached DMA region"
        default DMA_UNCACHED_1M

-       depends on BFIN_DMA_5XX

 config DMA_UNCACHED_4M
        bool "Enable 4M DMA region"
 config DMA_UNCACHED_2M
 config DMA_UNCACHED_4M
        bool "Enable 4M DMA region"
 config DMA_UNCACHED_2M


@@ -759,23 +907,43 @@ endchoice
 
 
 comment "Cache Support"
 
 
 comment "Cache Support"

+

 config BFIN_ICACHE
        bool "Enable ICACHE"
 config BFIN_ICACHE
        bool "Enable ICACHE"

+       default y
+config BFIN_ICACHE_LOCK
+       bool "Enable Instruction Cache Locking"
+       depends on BFIN_ICACHE
+       default n
+config BFIN_EXTMEM_ICACHEABLE
+       bool "Enable ICACHE for external memory"
+       depends on BFIN_ICACHE
+       default y
+config BFIN_L2_ICACHEABLE
+       bool "Enable ICACHE for L2 SRAM"
+       depends on BFIN_ICACHE
+       depends on BF54x || BF561
+       default n
+

 config BFIN_DCACHE
        bool "Enable DCACHE"
 config BFIN_DCACHE
        bool "Enable DCACHE"

+       default y

 config BFIN_DCACHE_BANKA
        bool "Enable only 16k BankA DCACHE - BankB is SRAM"
        depends on BFIN_DCACHE && !BF531
        default n
 config BFIN_DCACHE_BANKA
        bool "Enable only 16k BankA DCACHE - BankB is SRAM"
        depends on BFIN_DCACHE && !BF531
        default n

-config BFIN_ICACHE_LOCK
-       bool "Enable Instruction Cache Locking"
-
-choice
-       prompt "Policy"
+config BFIN_EXTMEM_DCACHEABLE
+       bool "Enable DCACHE for external memory"

        depends on BFIN_DCACHE
        depends on BFIN_DCACHE

-       default BFIN_WB
-config BFIN_WB
+       default y
+choice
+       prompt "External memory DCACHE policy"
+       depends on BFIN_EXTMEM_DCACHEABLE
+       default BFIN_EXTMEM_WRITEBACK if !SMP
+       default BFIN_EXTMEM_WRITETHROUGH if SMP
+config BFIN_EXTMEM_WRITEBACK

        bool "Write back"
        bool "Write back"

+       depends on !SMP

        help
          Write Back Policy:
            Cached data will be written back to SDRAM only when needed.
        help
          Write Back Policy:
            Cached data will be written back to SDRAM only when needed.


@@ -791,7 +959,7 @@ config BFIN_WB
          If you are unsure of the options and you want to be safe,
          then go with Write Through.
 
          If you are unsure of the options and you want to be safe,
          then go with Write Through.
 

-config BFIN_WT
+config BFIN_EXTMEM_WRITETHROUGH

        bool "Write through"
        help
          Write Back Policy:
        bool "Write through"
        help
          Write Back Policy:


@@ -810,13 +978,26 @@ config BFIN_WT
 
 endchoice
 
 
 endchoice
 

-config BFIN_L2_CACHEABLE
-       bool "Cache L2 SRAM"
-       depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
+config BFIN_L2_DCACHEABLE
+       bool "Enable DCACHE for L2 SRAM"
+       depends on BFIN_DCACHE
+       depends on BF54x || BF561

        default n
        default n

-       help
-         Select to make L2 SRAM cacheable in L1 data and instruction cache.
+choice
+       prompt "L2 SRAM DCACHE policy"
+       depends on BFIN_L2_DCACHEABLE
+       default BFIN_L2_WRITEBACK
+config BFIN_L2_WRITEBACK
+       bool "Write back"
+       depends on !SMP
+
+config BFIN_L2_WRITETHROUGH
+       bool "Write through"
+       depends on !SMP
+endchoice
+

 
 

+comment "Memory Protection Unit"

 config MPU
        bool "Enable the memory protection unit (EXPERIMENTAL)"
        default n
 config MPU
        bool "Enable the memory protection unit (EXPERIMENTAL)"
        default n


@@ -825,7 +1006,7 @@ config MPU
          memory they do not own.  This comes at a performance penalty
          and is recommended only for debugging.
 
          memory they do not own.  This comes at a performance penalty
          and is recommended only for debugging.
 

-comment "Asynchonous Memory Configuration"
+comment "Asynchronous Memory Configuration"

 
 menu "EBIU_AMGCTL Global Control"
 config C_AMCKEN
 
 menu "EBIU_AMGCTL Global Control"
 config C_AMCKEN


@@ -857,7 +1038,7 @@ config C_B3PEN
        default n
 
 choice
        default n
 
 choice

-       prompt"Enable Asynchonous Memory Banks"
+       prompt "Enable Asynchronous Memory Banks"

        default C_AMBEN_ALL
 
 config C_AMBEN
        default C_AMBEN_ALL
 
 config C_AMBEN


@@ -879,21 +1060,34 @@ endmenu
 
 menu "EBIU_AMBCTL Control"
 config BANK_0
 
 menu "EBIU_AMBCTL Control"
 config BANK_0

-       hex "Bank 0"
+       hex "Bank 0 (AMBCTL0.L)"

        default 0x7BB0
        default 0x7BB0

+       help
+         These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
+         used to control the Asynchronous Memory Bank 0 settings.

 
 config BANK_1
 
 config BANK_1

-       hex "Bank 1"
+       hex "Bank 1 (AMBCTL0.H)"

        default 0x7BB0
        default 0x5558 if BF54x
        default 0x7BB0
        default 0x5558 if BF54x

+       help
+         These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
+         used to control the Asynchronous Memory Bank 1 settings.

 
 config BANK_2
 
 config BANK_2

-       hex "Bank 2"
+       hex "Bank 2 (AMBCTL1.L)"

        default 0x7BB0
        default 0x7BB0

+       help
+         These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
+         used to control the Asynchronous Memory Bank 2 settings.

 
 config BANK_3
 
 config BANK_3

-       hex "Bank 3"
+       hex "Bank 3 (AMBCTL1.H)"

        default 0x99B3
        default 0x99B3

+       help
+         These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
+         used to control the Asynchronous Memory Bank 3 settings.
+

 endmenu
 
 config EBIU_MBSCTLVAL
 endmenu
 
 config EBIU_MBSCTLVAL


@@ -997,12 +1191,13 @@ endchoice
 
 config PM_WAKEUP_BY_GPIO
        bool "Allow Wakeup from Standby by GPIO"
 
 config PM_WAKEUP_BY_GPIO
        bool "Allow Wakeup from Standby by GPIO"

+       depends on PM && !BF54x

 
 config PM_WAKEUP_GPIO_NUMBER
        int "GPIO number"
        range 0 47
        depends on PM_WAKEUP_BY_GPIO
 
 config PM_WAKEUP_GPIO_NUMBER
        int "GPIO number"
        range 0 47
        depends on PM_WAKEUP_BY_GPIO

-       default 2 if BFIN537_STAMP
+       default 2

 
 choice
        prompt "GPIO Polarity"
 
 choice
        prompt "GPIO Polarity"


@@ -1025,7 +1220,7 @@ comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
 
 config PM_BFIN_WAKE_PH6
        bool "Allow Wake-Up from on-chip PHY or PH6 GP"
 
 config PM_BFIN_WAKE_PH6
        bool "Allow Wake-Up from on-chip PHY or PH6 GP"

-       depends on PM && (BF52x || BF534 || BF536 || BF537)
+       depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)

        default n
        help
          Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
        default n
        help
          Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)


@@ -1036,21 +1231,33 @@ config PM_BFIN_WAKE_GP
        default n
        help
          Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
        default n
        help
          Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)

+         (all processors, except ADSP-BF549). This option sets
+         the general-purpose wake-up enable (GPWE) control bit to enable
+         wake-up upon detection of an active low signal on the /GPW (PH7) pin.
+         On ADSP-BF549 this option enables the the same functionality on the
+         /MRXON pin also PH7.
+

 endmenu
 
 menu "CPU Frequency scaling"
 
 source "drivers/cpufreq/Kconfig"
 
 endmenu
 
 menu "CPU Frequency scaling"
 
 source "drivers/cpufreq/Kconfig"
 

+config BFIN_CPU_FREQ
+       bool
+       depends on CPU_FREQ
+       select CPU_FREQ_TABLE
+       default y
+

 config CPU_VOLTAGE
        bool "CPU Voltage scaling"
 config CPU_VOLTAGE
        bool "CPU Voltage scaling"

-       depends on EXPERIMENTAL 
+       depends on EXPERIMENTAL

        depends on CPU_FREQ
        default n
        help
          Say Y here if you want CPU voltage scaling according to the CPU frequency.
          This option violates the PLL BYPASS recommendation in the Blackfin Processor
        depends on CPU_FREQ
        default n
        help
          Say Y here if you want CPU voltage scaling according to the CPU frequency.
          This option violates the PLL BYPASS recommendation in the Blackfin Processor

-         manuals. There is a theoretical risk that during VDDINT transitions 
+         manuals. There is a theoretical risk that during VDDINT transitions

          the PLL may unlock.
 
 endmenu
          the PLL may unlock.
 
 endmenu