ARM: Add Versatile Express CA9x4 processor support

[safe/jmp/linux-2.6] / arch / arm / mm / Kconfig

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 3b90051..270c8e2 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -1,24 +1,19 @@
 comment "Processor Type"
 
 comment "Processor Type"
 

-config CPU_32
-       bool
-       default y
-

 # Select CPU types depending on the architecture selected.  This selects
 # which CPUs we support in the kernel image, and the compiler instruction
 # optimiser behaviour.
 
 # ARM610
 config CPU_ARM610
 # Select CPU types depending on the architecture selected.  This selects
 # which CPUs we support in the kernel image, and the compiler instruction
 # optimiser behaviour.
 
 # ARM610
 config CPU_ARM610

-       bool "Support ARM610 processor"
-       depends on ARCH_RPC
+       bool "Support ARM610 processor" if ARCH_RPC

        select CPU_32v3
        select CPU_CACHE_V3
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_COPY_V3 if MMU
        select CPU_TLB_V3 if MMU
        select CPU_32v3
        select CPU_CACHE_V3
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_COPY_V3 if MMU
        select CPU_TLB_V3 if MMU

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        help
          The ARM610 is the successor to the ARM3 processor
          and was produced by VLSI Technology Inc.
        help
          The ARM610 is the successor to the ARM3 processor
          and was produced by VLSI Technology Inc.


@@ -32,7 +27,7 @@ config CPU_ARM7TDMI
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_LV4T
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_LV4T

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_V4
        help
          A 32-bit RISC microprocessor based on the ARM7 processor core
        select CPU_CACHE_V4
        help
          A 32-bit RISC microprocessor based on the ARM7 processor core


@@ -43,15 +38,14 @@ config CPU_ARM7TDMI
 
 # ARM710
 config CPU_ARM710
 
 # ARM710
 config CPU_ARM710

-       bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
-       default y if ARCH_CLPS7500
+       bool "Support ARM710 processor" if ARCH_RPC

        select CPU_32v3
        select CPU_CACHE_V3
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_COPY_V3 if MMU
        select CPU_TLB_V3 if MMU
        select CPU_32v3
        select CPU_CACHE_V3
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_COPY_V3 if MMU
        select CPU_TLB_V3 if MMU

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        help
          A 32-bit RISC microprocessor based on the ARM7 processor core
          designed by Advanced RISC Machines Ltd. The ARM710 is the
        help
          A 32-bit RISC microprocessor based on the ARM7 processor core
          designed by Advanced RISC Machines Ltd. The ARM710 is the


@@ -63,11 +57,10 @@ config CPU_ARM710
 
 # ARM720T
 config CPU_ARM720T
 
 # ARM720T
 config CPU_ARM720T

-       bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
-       default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
+       bool "Support ARM720T processor" if ARCH_INTEGRATOR

        select CPU_32v4T
        select CPU_ABRT_LV4T
        select CPU_32v4T
        select CPU_ABRT_LV4T

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_V4
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_CACHE_V4
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU


@@ -86,7 +79,7 @@ config CPU_ARM740T
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_LV4T
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_LV4T

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_V3     # although the core is v4t
        select CPU_CP15_MPU
        help
        select CPU_CACHE_V3     # although the core is v4t
        select CPU_CP15_MPU
        help


@@ -103,7 +96,7 @@ config CPU_ARM9TDMI
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_NOMMU
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_NOMMU

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_V4
        help
          A 32-bit RISC microprocessor based on the ARM9 processor core
        select CPU_CACHE_V4
        help
          A 32-bit RISC microprocessor based on the ARM9 processor core


@@ -114,12 +107,10 @@ config CPU_ARM9TDMI
 
 # ARM920T
 config CPU_ARM920T
 
 # ARM920T
 config CPU_ARM920T

-       bool "Support ARM920T processor"
-       depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
-       default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
+       bool "Support ARM920T processor" if ARCH_INTEGRATOR

        select CPU_32v4T
        select CPU_ABRT_EV4T
        select CPU_32v4T
        select CPU_ABRT_EV4T

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_V4WT
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_CACHE_V4WT
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU


@@ -127,10 +118,7 @@ config CPU_ARM920T
        select CPU_TLB_V4WBI if MMU
        help
          The ARM920T is licensed to be produced by numerous vendors,
        select CPU_TLB_V4WBI if MMU
        help
          The ARM920T is licensed to be produced by numerous vendors,

-         and is used in the Maverick EP9312 and the Samsung S3C2410.
-
-         More information on the Maverick EP9312 at
-         <http://linuxdevices.com/products/PD2382866068.html>.
+         and is used in the Cirrus EP93xx and the Samsung S3C2410.

 
          Say Y if you want support for the ARM920T processor.
          Otherwise, say N.
 
          Say Y if you want support for the ARM920T processor.
          Otherwise, say N.


@@ -138,11 +126,9 @@ config CPU_ARM920T
 # ARM922T
 config CPU_ARM922T
        bool "Support ARM922T processor" if ARCH_INTEGRATOR
 # ARM922T
 config CPU_ARM922T
        bool "Support ARM922T processor" if ARCH_INTEGRATOR

-       depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695
-       default y if ARCH_LH7A40X || ARCH_KS8695

        select CPU_32v4T
        select CPU_ABRT_EV4T
        select CPU_32v4T
        select CPU_ABRT_EV4T

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_V4WT
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_CACHE_V4WT
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU


@@ -159,11 +145,9 @@ config CPU_ARM922T
 # ARM925T
 config CPU_ARM925T
        bool "Support ARM925T processor" if ARCH_OMAP1
 # ARM925T
 config CPU_ARM925T
        bool "Support ARM925T processor" if ARCH_OMAP1

-       depends on ARCH_OMAP15XX
-       default y if ARCH_OMAP15XX

        select CPU_32v4T
        select CPU_ABRT_EV4T
        select CPU_32v4T
        select CPU_ABRT_EV4T

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_V4WT
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_CACHE_V4WT
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU


@@ -179,12 +163,10 @@ config CPU_ARM925T
 
 # ARM926T
 config CPU_ARM926T
 
 # ARM926T
 config CPU_ARM926T

-       bool "Support ARM926T processor"
-       depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
-       default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
+       bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB

        select CPU_32v5
        select CPU_ABRT_EV5TJ
        select CPU_32v5
        select CPU_ABRT_EV5TJ

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_COPY_V4WB if MMU
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_COPY_V4WB if MMU


@@ -197,13 +179,31 @@ config CPU_ARM926T
          Say Y if you want support for the ARM926T processor.
          Otherwise, say N.
 
          Say Y if you want support for the ARM926T processor.
          Otherwise, say N.
 

+# FA526
+config CPU_FA526
+       bool
+       select CPU_32v4
+       select CPU_ABRT_EV4
+       select CPU_PABRT_LEGACY
+       select CPU_CACHE_VIVT
+       select CPU_CP15_MMU
+       select CPU_CACHE_FA
+       select CPU_COPY_FA if MMU
+       select CPU_TLB_FA if MMU
+       help
+         The FA526 is a version of the ARMv4 compatible processor with
+         Branch Target Buffer, Unified TLB and cache line size 16.
+
+         Say Y if you want support for the FA526 processor.
+         Otherwise, say N.
+

 # ARM940T
 config CPU_ARM940T
        bool "Support ARM940T processor" if ARCH_INTEGRATOR
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_NOMMU
 # ARM940T
 config CPU_ARM940T
        bool "Support ARM940T processor" if ARCH_INTEGRATOR
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_NOMMU

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_VIVT
        select CPU_CP15_MPU
        help
        select CPU_CACHE_VIVT
        select CPU_CP15_MPU
        help


@@ -221,7 +221,7 @@ config CPU_ARM946E
        depends on !MMU
        select CPU_32v5
        select CPU_ABRT_NOMMU
        depends on !MMU
        select CPU_32v5
        select CPU_ABRT_NOMMU

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_VIVT
        select CPU_CP15_MPU
        help
        select CPU_CACHE_VIVT
        select CPU_CP15_MPU
        help


@@ -234,11 +234,10 @@ config CPU_ARM946E
 
 # ARM1020 - needs validating
 config CPU_ARM1020
 
 # ARM1020 - needs validating
 config CPU_ARM1020

-       bool "Support ARM1020T (rev 0) processor"
-       depends on ARCH_INTEGRATOR
+       bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR

        select CPU_32v5
        select CPU_ABRT_EV4T
        select CPU_32v5
        select CPU_ABRT_EV4T

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_V4WT
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_CACHE_V4WT
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU


@@ -253,11 +252,10 @@ config CPU_ARM1020
 
 # ARM1020E - needs validating
 config CPU_ARM1020E
 
 # ARM1020E - needs validating
 config CPU_ARM1020E

-       bool "Support ARM1020E processor"
-       depends on ARCH_INTEGRATOR
+       bool "Support ARM1020E processor" if ARCH_INTEGRATOR

        select CPU_32v5
        select CPU_ABRT_EV4T
        select CPU_32v5
        select CPU_ABRT_EV4T

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_V4WT
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_CACHE_V4WT
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU


@@ -267,11 +265,10 @@ config CPU_ARM1020E
 
 # ARM1022E
 config CPU_ARM1022
 
 # ARM1022E
 config CPU_ARM1022

-       bool "Support ARM1022E processor"
-       depends on ARCH_INTEGRATOR
+       bool "Support ARM1022E processor" if ARCH_INTEGRATOR

        select CPU_32v5
        select CPU_ABRT_EV4T
        select CPU_32v5
        select CPU_ABRT_EV4T

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_COPY_V4WB if MMU # can probably do better
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_COPY_V4WB if MMU # can probably do better


@@ -286,11 +283,10 @@ config CPU_ARM1022
 
 # ARM1026EJ-S
 config CPU_ARM1026
 
 # ARM1026EJ-S
 config CPU_ARM1026

-       bool "Support ARM1026EJ-S processor"
-       depends on ARCH_INTEGRATOR
+       bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR

        select CPU_32v5
        select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
        select CPU_32v5
        select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_COPY_V4WB if MMU # can probably do better
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_COPY_V4WB if MMU # can probably do better


@@ -304,12 +300,11 @@ config CPU_ARM1026
 
 # SA110
 config CPU_SA110
 
 # SA110
 config CPU_SA110

-       bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
-       default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
+       bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC

        select CPU_32v3 if ARCH_RPC
        select CPU_32v4 if !ARCH_RPC
        select CPU_ABRT_EV4
        select CPU_32v3 if ARCH_RPC
        select CPU_32v4 if !ARCH_RPC
        select CPU_ABRT_EV4

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_V4WB
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_CACHE_V4WB
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU


@@ -327,11 +322,9 @@ config CPU_SA110
 # SA1100
 config CPU_SA1100
        bool
 # SA1100
 config CPU_SA1100
        bool

-       depends on ARCH_SA1100
-       default y

        select CPU_32v4
        select CPU_ABRT_EV4
        select CPU_32v4
        select CPU_ABRT_EV4

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_V4WB
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_CACHE_V4WB
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU


@@ -340,11 +333,9 @@ config CPU_SA1100
 # XScale
 config CPU_XSCALE
        bool
 # XScale
 config CPU_XSCALE
        bool

-       depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000
-       default y

        select CPU_32v5
        select CPU_ABRT_EV5T
        select CPU_32v5
        select CPU_ABRT_EV5T

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_TLB_V4WBI if MMU
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_TLB_V4WBI if MMU


@@ -352,24 +343,31 @@ config CPU_XSCALE
 # XScale Core Version 3
 config CPU_XSC3
        bool
 # XScale Core Version 3
 config CPU_XSC3
        bool

-       depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx
-       default y

        select CPU_32v5
        select CPU_ABRT_EV5T
        select CPU_32v5
        select CPU_ABRT_EV5T

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_TLB_V4WBI if MMU
        select IO_36
 
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_TLB_V4WBI if MMU
        select IO_36
 

+# Marvell PJ1 (Mohawk)
+config CPU_MOHAWK
+       bool
+       select CPU_32v5
+       select CPU_ABRT_EV5T
+       select CPU_PABRT_LEGACY
+       select CPU_CACHE_VIVT
+       select CPU_CP15_MMU
+       select CPU_TLB_V4WBI if MMU
+       select CPU_COPY_V4WB if MMU
+

 # Feroceon
 config CPU_FEROCEON
        bool
 # Feroceon
 config CPU_FEROCEON
        bool

-       depends on ARCH_ORION5X || ARCH_LOKI
-       default y

        select CPU_32v5
        select CPU_ABRT_EV5T
        select CPU_32v5
        select CPU_ABRT_EV5T

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY

        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_COPY_FEROCEON if MMU
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_COPY_FEROCEON if MMU


@@ -386,13 +384,10 @@ config CPU_FEROCEON_OLD_ID
 
 # ARMv6
 config CPU_V6
 
 # ARMv6
 config CPU_V6

-       bool "Support ARM V6 processor"
-       depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
-       default y if ARCH_MX3
-       default y if ARCH_MSM7X00A
+       bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE

        select CPU_32v6
        select CPU_ABRT_EV6
        select CPU_32v6
        select CPU_ABRT_EV6

-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_V6

        select CPU_CACHE_V6
        select CPU_CACHE_VIPT
        select CPU_CP15_MMU
        select CPU_CACHE_V6
        select CPU_CACHE_VIPT
        select CPU_CP15_MMU


@@ -404,7 +399,7 @@ config CPU_V6
 config CPU_32v6K
        bool "Support ARM V6K processor extensions" if !SMP
        depends on CPU_V6
 config CPU_32v6K
        bool "Support ARM V6K processor extensions" if !SMP
        depends on CPU_V6

-       default y if SMP && !ARCH_MX3
+       default y if SMP && !(ARCH_MX3 || ARCH_OMAP2)

        help
          Say Y here if your ARMv6 processor supports the 'K' extension.
          This enables the kernel to use some instructions not present
        help
          Say Y here if your ARMv6 processor supports the 'K' extension.
          This enables the kernel to use some instructions not present


@@ -414,12 +409,11 @@ config CPU_32v6K
 
 # ARMv7
 config CPU_V7
 
 # ARMv7
 config CPU_V7

-       bool "Support ARM V7 processor"
-       depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB
-       select CPU_32v6K
+       bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
+       select CPU_32v6K if !ARCH_OMAP2

        select CPU_32v7
        select CPU_ABRT_EV7
        select CPU_32v7
        select CPU_ABRT_EV7

-       select CPU_PABRT_IFAR
+       select CPU_PABRT_V7

        select CPU_CACHE_V7
        select CPU_CACHE_VIPT
        select CPU_CP15_MMU
        select CPU_CACHE_V7
        select CPU_CACHE_VIPT
        select CPU_CP15_MMU


@@ -481,10 +475,13 @@ config CPU_ABRT_EV6
 config CPU_ABRT_EV7
        bool
 
 config CPU_ABRT_EV7
        bool
 

-config CPU_PABRT_IFAR
+config CPU_PABRT_LEGACY

        bool
 
        bool
 

-config CPU_PABRT_NOIFAR
+config CPU_PABRT_V6
+       bool
+
+config CPU_PABRT_V7

        bool
 
 # The cache model
        bool
 
 # The cache model


@@ -512,6 +509,9 @@ config CPU_CACHE_VIVT
 config CPU_CACHE_VIPT
        bool
 
 config CPU_CACHE_VIPT
        bool
 

+config CPU_CACHE_FA
+       bool
+

 if MMU
 # The copy-page model
 config CPU_COPY_V3
 if MMU
 # The copy-page model
 config CPU_COPY_V3


@@ -526,6 +526,9 @@ config CPU_COPY_V4WB
 config CPU_COPY_FEROCEON
        bool
 
 config CPU_COPY_FEROCEON
        bool
 

+config CPU_COPY_FA
+       bool
+

 config CPU_COPY_V6
        bool
 
 config CPU_COPY_V6
        bool
 


@@ -556,6 +559,13 @@ config CPU_TLB_FEROCEON
        help
          Feroceon TLB (v4wbi with non-outer-cachable page table walks).
 
        help
          Feroceon TLB (v4wbi with non-outer-cachable page table walks).
 

+config CPU_TLB_FA
+       bool
+       help
+         Faraday ARM FA526 architecture, unified TLB with writeback cache
+         and invalidate instruction cache entry. Branch target buffer is
+         also supported.
+

 config CPU_TLB_V6
        bool
 
 config CPU_TLB_V6
        bool
 


@@ -597,7 +607,7 @@ comment "Processor Features"
 
 config ARM_THUMB
        bool "Support Thumb user binaries"
 
 config ARM_THUMB
        bool "Support Thumb user binaries"

-       depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON
+       depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON

        default y
        help
          Say Y if you want to include kernel support for running user space
        default y
        help
          Say Y if you want to include kernel support for running user space


@@ -625,10 +635,23 @@ config CPU_BIG_ENDIAN
          port must properly enable any big-endian related features
          of your chipset/board/processor.
 
          port must properly enable any big-endian related features
          of your chipset/board/processor.
 

+config CPU_ENDIAN_BE8
+       bool
+       depends on CPU_BIG_ENDIAN
+       default CPU_V6 || CPU_V7
+       help
+         Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
+
+config CPU_ENDIAN_BE32
+       bool
+       depends on CPU_BIG_ENDIAN
+       default !CPU_ENDIAN_BE8
+       help
+         Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
+

 config CPU_HIGH_VECTOR
        depends on !MMU && CPU_CP15 && !CPU_ARM740T
        bool "Select the High exception vector"
 config CPU_HIGH_VECTOR
        depends on !MMU && CPU_CP15 && !CPU_ARM740T
        bool "Select the High exception vector"

-       default n

        help
          Say Y here to select high exception vector(0xFFFF0000~).
          The exception vector can be vary depending on the platform
        help
          Say Y here to select high exception vector(0xFFFF0000~).
          The exception vector can be vary depending on the platform


@@ -666,7 +689,7 @@ config CPU_DCACHE_SIZE
 
 config CPU_DCACHE_WRITETHROUGH
        bool "Force write through D-cache"
 
 config CPU_DCACHE_WRITETHROUGH
        bool "Force write through D-cache"

-       depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
+       depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE

        default y if CPU_ARM925T
        help
          Say Y here to use the data cache in writethrough mode. Unless you
        default y if CPU_ARM925T
        help
          Say Y here to use the data cache in writethrough mode. Unless you


@@ -681,7 +704,7 @@ config CPU_CACHE_ROUND_ROBIN
 
 config CPU_BPREDICT_DISABLE
        bool "Disable branch prediction"
 
 config CPU_BPREDICT_DISABLE
        bool "Disable branch prediction"

-       depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
+       depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526

        help
          Say Y here to disable branch prediction.  If unsure, say N.
 
        help
          Say Y here to disable branch prediction.  If unsure, say N.
 


@@ -712,20 +735,50 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
 
 config OUTER_CACHE
        bool
 
 config OUTER_CACHE
        bool

-       default n

 
 config CACHE_FEROCEON_L2
        bool "Enable the Feroceon L2 cache controller"
 
 config CACHE_FEROCEON_L2
        bool "Enable the Feroceon L2 cache controller"

-       depends on FOOBAR
+       depends on ARCH_KIRKWOOD || ARCH_MV78XX0

        default y
        select OUTER_CACHE
        help
          This option enables the Feroceon L2 cache controller.
 
        default y
        select OUTER_CACHE
        help
          This option enables the Feroceon L2 cache controller.
 

+config CACHE_FEROCEON_L2_WRITETHROUGH
+       bool "Force Feroceon L2 cache write through"
+       depends on CACHE_FEROCEON_L2
+       help
+         Say Y here to use the Feroceon L2 cache in writethrough mode.
+         Unless you specifically require this, say N for writeback mode.
+

 config CACHE_L2X0
        bool "Enable the L2x0 outer cache controller"
 config CACHE_L2X0
        bool "Enable the L2x0 outer cache controller"

-       depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
+       depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
+                  REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
+                  ARCH_NOMADIK || ARCH_OMAP4 || ARCH_VEXPRESS_CA9X4

        default y
        select OUTER_CACHE
        help
          This option enables the L2x0 PrimeCell.
        default y
        select OUTER_CACHE
        help
          This option enables the L2x0 PrimeCell.

+
+config CACHE_TAUROS2
+       bool "Enable the Tauros2 L2 cache controller"
+       depends on ARCH_DOVE
+       default y
+       select OUTER_CACHE
+       help
+         This option enables the Tauros2 L2 cache controller (as
+         found on PJ1/PJ4).
+
+config CACHE_XSC3L2
+       bool "Enable the L2 cache on XScale3"
+       depends on CPU_XSC3
+       default y
+       select OUTER_CACHE
+       help
+         This option enables the L2 cache on XScale3.
+
+config ARM_L1_CACHE_SHIFT
+       int
+       default 6 if ARM_L1_CACHE_SHIFT_6
+       default 5