+ * XOR engine
+ ****************************************************************************/
+struct mv_xor_platform_shared_data orion5x_xor_shared_data = {
+ .dram = &orion5x_mbus_dram_info,
+};
+
+static struct resource orion5x_xor_shared_resources[] = {
+ {
+ .name = "xor low",
+ .start = ORION5X_XOR_PHYS_BASE,
+ .end = ORION5X_XOR_PHYS_BASE + 0xff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "xor high",
+ .start = ORION5X_XOR_PHYS_BASE + 0x200,
+ .end = ORION5X_XOR_PHYS_BASE + 0x2ff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device orion5x_xor_shared = {
+ .name = MV_XOR_SHARED_NAME,
+ .id = 0,
+ .dev = {
+ .platform_data = &orion5x_xor_shared_data,
+ },
+ .num_resources = ARRAY_SIZE(orion5x_xor_shared_resources),
+ .resource = orion5x_xor_shared_resources,
+};
+
+static u64 orion5x_xor_dmamask = DMA_BIT_MASK(32);
+
+static struct resource orion5x_xor0_resources[] = {
+ [0] = {
+ .start = IRQ_ORION5X_XOR0,
+ .end = IRQ_ORION5X_XOR0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct mv_xor_platform_data orion5x_xor0_data = {
+ .shared = &orion5x_xor_shared,
+ .hw_id = 0,
+ .pool_size = PAGE_SIZE,
+};
+
+static struct platform_device orion5x_xor0_channel = {
+ .name = MV_XOR_NAME,
+ .id = 0,
+ .num_resources = ARRAY_SIZE(orion5x_xor0_resources),
+ .resource = orion5x_xor0_resources,
+ .dev = {
+ .dma_mask = &orion5x_xor_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(64),
+ .platform_data = (void *)&orion5x_xor0_data,
+ },
+};
+
+static struct resource orion5x_xor1_resources[] = {
+ [0] = {
+ .start = IRQ_ORION5X_XOR1,
+ .end = IRQ_ORION5X_XOR1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct mv_xor_platform_data orion5x_xor1_data = {
+ .shared = &orion5x_xor_shared,
+ .hw_id = 1,
+ .pool_size = PAGE_SIZE,
+};
+
+static struct platform_device orion5x_xor1_channel = {
+ .name = MV_XOR_NAME,
+ .id = 1,
+ .num_resources = ARRAY_SIZE(orion5x_xor1_resources),
+ .resource = orion5x_xor1_resources,
+ .dev = {
+ .dma_mask = &orion5x_xor_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(64),
+ .platform_data = (void *)&orion5x_xor1_data,
+ },
+};
+
+void __init orion5x_xor_init(void)
+{
+ platform_device_register(&orion5x_xor_shared);
+
+ /*
+ * two engines can't do memset simultaneously, this limitation
+ * satisfied by removing memset support from one of the engines.
+ */
+ dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
+ dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
+ platform_device_register(&orion5x_xor0_channel);
+
+ dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
+ dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
+ dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
+ platform_device_register(&orion5x_xor1_channel);
+}
+
+static struct resource orion5x_crypto_res[] = {
+ {
+ .name = "regs",
+ .start = ORION5X_CRYPTO_PHYS_BASE,
+ .end = ORION5X_CRYPTO_PHYS_BASE + 0xffff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "sram",
+ .start = ORION5X_SRAM_PHYS_BASE,
+ .end = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "crypto interrupt",
+ .start = IRQ_ORION5X_CESA,
+ .end = IRQ_ORION5X_CESA,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device orion5x_crypto_device = {
+ .name = "mv_crypto",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(orion5x_crypto_res),
+ .resource = orion5x_crypto_res,
+};
+
+int __init orion5x_crypto_init(void)
+{
+ int ret;
+
+ ret = orion5x_setup_sram_win();
+ if (ret)
+ return ret;
+
+ return platform_device_register(&orion5x_crypto_device);
+}
+
+/*****************************************************************************
+ * Watchdog
+ ****************************************************************************/
+static struct orion_wdt_platform_data orion5x_wdt_data = {
+ .tclk = 0,
+};
+
+static struct platform_device orion5x_wdt_device = {
+ .name = "orion_wdt",
+ .id = -1,
+ .dev = {
+ .platform_data = &orion5x_wdt_data,
+ },
+ .num_resources = 0,
+};
+
+void __init orion5x_wdt_init(void)
+{
+ orion5x_wdt_data.tclk = orion5x_tclk;
+ platform_device_register(&orion5x_wdt_device);
+}
+
+
+/*****************************************************************************