2 * Driver for DBRI sound chip found on Sparcs.
3 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
5 * Based entirely upon drivers/sbus/audio/dbri.c which is:
6 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
7 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
9 * This is the lowlevel driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
10 * on Sun SPARCstation 10, 20, LX and Voyager models.
12 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
13 * data time multiplexer with ISDN support (aka T7259)
14 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
15 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
17 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Tranceiver" from
18 * Sparc Technology Business (courtesy of Sun Support)
19 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
20 * available from the Lucent (formarly AT&T microelectronics) home
22 * - http://www.freesoft.org/Linux/DBRI/
23 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
24 * Interfaces: CHI, Audio In & Out, 2 bits parallel
25 * Documentation: from the Crystal Semiconductor home page.
27 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
28 * memory and a serial device (long pipes, nr 0-15) or between two serial
29 * devices (short pipes, nr 16-31), or simply send a fixed data to a serial
30 * device (short pipes).
31 * A timeslot defines the bit-offset and nr of bits read from a serial device.
32 * The timeslots are linked to 6 circular lists, one for each direction for
33 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
34 * (the second one is a monitor/tee pipe, valid only for serial input).
36 * The mmcodec is connected via the CHI bus and needs the data & some
37 * parameters (volume, output selection) timemultiplexed in 8 byte
38 * chunks. It also has a control mode, which serves for audio format setting.
40 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
41 * the same CHI bus, so I thought perhaps it is possible to use the onboard
42 * & the speakerbox codec simultanously, giving 2 (not very independent :-)
43 * audio devices. But the SUN HW group decided against it, at least on my
44 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
47 * I've tried to stick to the following function naming conventions:
49 * cs4215_* CS4215 codec specific stuff
50 * dbri_* DBRI high-level stuff
51 * other DBRI low-level stuff
54 #include <sound/driver.h>
55 #include <linux/interrupt.h>
56 #include <linux/delay.h>
58 #include <sound/core.h>
59 #include <sound/pcm.h>
60 #include <sound/pcm_params.h>
61 #include <sound/info.h>
62 #include <sound/control.h>
63 #include <sound/initval.h>
68 #include <asm/atomic.h>
70 MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
71 MODULE_DESCRIPTION("Sun DBRI");
72 MODULE_LICENSE("GPL");
73 MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
75 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
76 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
77 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
79 module_param_array(index, int, NULL, 0444);
80 MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
81 module_param_array(id, charp, NULL, 0444);
82 MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
83 module_param_array(enable, bool, NULL, 0444);
84 MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
95 static int dbri_debug;
96 module_param(dbri_debug, int, 0644);
97 MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
100 static char *cmds[] = {
101 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
102 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
105 #define dprintk(a, x...) if(dbri_debug & a) printk(KERN_DEBUG x)
108 #define dprintk(a, x...)
110 #endif /* DBRI_DEBUG */
112 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
116 /***************************************************************************
117 CS4215 specific definitions and structures
118 ****************************************************************************/
121 __u8 data[4]; /* Data mode: Time slots 5-8 */
122 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
124 __u8 offset; /* Bit offset from frame sync to time slot 1 */
125 volatile __u32 status;
126 volatile __u32 version;
127 __u8 precision; /* In bits, either 8 or 16 */
128 __u8 channels; /* 1 or 2 */
135 /* Time Slot 1, Status register */
136 #define CS4215_CLB (1<<2) /* Control Latch Bit */
137 #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
138 /* 0: line: 2.8V, speaker 8V */
139 #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
140 #define CS4215_RSRVD_1 (1<<5)
142 /* Time Slot 2, Data Format Register */
143 #define CS4215_DFR_LINEAR16 0
144 #define CS4215_DFR_ULAW 1
145 #define CS4215_DFR_ALAW 2
146 #define CS4215_DFR_LINEAR8 3
147 #define CS4215_DFR_STEREO (1<<2)
153 { 8000, (1 << 4), (0 << 3) },
154 { 16000, (1 << 4), (1 << 3) },
155 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
156 { 32000, (1 << 4), (3 << 3) },
157 /* { NA, (1 << 4), (4 << 3) }, */
158 /* { NA, (1 << 4), (5 << 3) }, */
159 { 48000, (1 << 4), (6 << 3) },
160 { 9600, (1 << 4), (7 << 3) },
161 { 5513, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
162 { 11025, (2 << 4), (1 << 3) },
163 { 18900, (2 << 4), (2 << 3) },
164 { 22050, (2 << 4), (3 << 3) },
165 { 37800, (2 << 4), (4 << 3) },
166 { 44100, (2 << 4), (5 << 3) },
167 { 33075, (2 << 4), (6 << 3) },
168 { 6615, (2 << 4), (7 << 3) },
172 #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
174 #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
176 /* Time Slot 3, Serial Port Control register */
177 #define CS4215_XEN (1<<0) /* 0: Enable serial output */
178 #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
179 #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
180 #define CS4215_BSEL_128 (1<<2)
181 #define CS4215_BSEL_256 (2<<2)
182 #define CS4215_MCK_MAST (0<<4) /* Master clock */
183 #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
184 #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
185 #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
186 #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
188 /* Time Slot 4, Test Register */
189 #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
190 #define CS4215_ENL (1<<1) /* Enable Loopback Testing */
192 /* Time Slot 5, Parallel Port Register */
193 /* Read only here and the same as the in data mode */
195 /* Time Slot 6, Reserved */
197 /* Time Slot 7, Version Register */
198 #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
200 /* Time Slot 8, Reserved */
205 /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
207 /* Time Slot 5, Output Setting */
208 #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
209 #define CS4215_LE (1<<6) /* Line Out Enable */
210 #define CS4215_HE (1<<7) /* Headphone Enable */
212 /* Time Slot 6, Output Setting */
213 #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
214 #define CS4215_SE (1<<6) /* Speaker Enable */
215 #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
217 /* Time Slot 7, Input Setting */
218 #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
219 #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
220 #define CS4215_OVR (1<<5) /* 1: Overrange condition occurred */
221 #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
222 #define CS4215_PIO1 (1<<7)
224 /* Time Slot 8, Input Setting */
225 #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
226 #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
228 /***************************************************************************
229 DBRI specific definitions and structures
230 ****************************************************************************/
232 /* DBRI main registers */
233 #define REG0 0x00UL /* Status and Control */
234 #define REG1 0x04UL /* Mode and Interrupt */
235 #define REG2 0x08UL /* Parallel IO */
236 #define REG3 0x0cUL /* Test */
237 #define REG8 0x20UL /* Command Queue Pointer */
238 #define REG9 0x24UL /* Interrupt Queue Pointer */
240 #define DBRI_NO_CMDS 64
241 #define DBRI_INT_BLK 64
242 #define DBRI_NO_DESCS 64
243 #define DBRI_NO_PIPES 32
245 #define DBRI_MM_ONB 1
250 #define DBRI_NO_STREAMS 2
252 /* One transmit/receive descriptor */
253 /* When ba != 0 descriptor is used */
255 volatile __u32 word1;
256 __u32 ba; /* Transmit/Receive Buffer Address */
257 __u32 nda; /* Next Descriptor Address */
258 volatile __u32 word4;
261 /* This structure is in a DMA region where it can accessed by both
262 * the CPU and the DBRI
265 volatile s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
266 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */
267 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
270 #define dbri_dma_off(member, elem) \
271 ((u32)(unsigned long) \
272 (&(((struct dbri_dma *)0)->member[elem])))
274 enum in_or_out { PIPEinput, PIPEoutput };
277 u32 sdp; /* SDP command word */
278 int nextpipe; /* Next pipe in linked list */
279 int cycle; /* Offset of timeslot (bits) */
280 int length; /* Length of timeslot (bits) */
281 int first_desc; /* Index of first descriptor */
282 int desc; /* Index of active descriptor */
283 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
286 /* Per stream (playback or record) information */
287 struct dbri_streaminfo {
288 struct snd_pcm_substream *substream;
289 u32 dvma_buffer; /* Device view of Alsa DMA buffer */
290 int left; /* # of bytes left in DMA buffer */
291 int size; /* Size of DMA buffer */
292 size_t offset; /* offset in user buffer */
293 int pipe; /* Data pipe used */
294 int left_gain; /* mixer elements */
298 /* This structure holds the information for both chips (DBRI & CS4215) */
300 struct snd_card *card; /* ALSA card */
302 int regs_size, irq; /* Needed for unload */
303 struct sbus_dev *sdev; /* SBUS device info */
306 struct dbri_dma *dma; /* Pointer to our DMA block */
307 u32 dma_dvma; /* DBRI visible DMA address */
309 void __iomem *regs; /* dbri HW regs */
310 int dbri_irqp; /* intr queue pointer */
311 int wait_send; /* sequence of command buffers send */
312 int wait_ackd; /* sequence of command buffers acknowledged */
314 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
315 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
321 struct cs4215 mm; /* mmcodec special info */
322 /* per stream (playback/record) info */
323 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
325 struct snd_dbri *next;
328 #define DBRI_MAX_VOLUME 63 /* Output volume */
329 #define DBRI_MAX_GAIN 15 /* Input gain */
331 /* DBRI Reg0 - Status Control Register - defines. (Page 17) */
332 #define D_P (1<<15) /* Program command & queue pointer valid */
333 #define D_G (1<<14) /* Allow 4-Word SBus Burst */
334 #define D_S (1<<13) /* Allow 16-Word SBus Burst */
335 #define D_E (1<<12) /* Allow 8-Word SBus Burst */
336 #define D_X (1<<7) /* Sanity Timer Disable */
337 #define D_T (1<<6) /* Permit activation of the TE interface */
338 #define D_N (1<<5) /* Permit activation of the NT interface */
339 #define D_C (1<<4) /* Permit activation of the CHI interface */
340 #define D_F (1<<3) /* Force Sanity Timer Time-Out */
341 #define D_D (1<<2) /* Disable Master Mode */
342 #define D_H (1<<1) /* Halt for Analysis */
343 #define D_R (1<<0) /* Soft Reset */
345 /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
346 #define D_LITTLE_END (1<<8) /* Byte Order */
347 #define D_BIG_END (0<<8) /* Byte Order */
348 #define D_MRR (1<<4) /* Multiple Error Ack on SBus (readonly) */
349 #define D_MLE (1<<3) /* Multiple Late Error on SBus (readonly) */
350 #define D_LBG (1<<2) /* Lost Bus Grant on SBus (readonly) */
351 #define D_MBE (1<<1) /* Burst Error on SBus (readonly) */
352 #define D_IR (1<<0) /* Interrupt Indicator (readonly) */
354 /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
355 #define D_ENPIO3 (1<<7) /* Enable Pin 3 */
356 #define D_ENPIO2 (1<<6) /* Enable Pin 2 */
357 #define D_ENPIO1 (1<<5) /* Enable Pin 1 */
358 #define D_ENPIO0 (1<<4) /* Enable Pin 0 */
359 #define D_ENPIO (0xf0) /* Enable all the pins */
360 #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
361 #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
362 #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
363 #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
365 /* DBRI Commands (Page 20) */
366 #define D_WAIT 0x0 /* Stop execution */
367 #define D_PAUSE 0x1 /* Flush long pipes */
368 #define D_JUMP 0x2 /* New command queue */
369 #define D_IIQ 0x3 /* Initialize Interrupt Queue */
370 #define D_REX 0x4 /* Report command execution via interrupt */
371 #define D_SDP 0x5 /* Setup Data Pipe */
372 #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
373 #define D_DTS 0x7 /* Define Time Slot */
374 #define D_SSP 0x8 /* Set short Data Pipe */
375 #define D_CHI 0x9 /* Set CHI Global Mode */
376 #define D_NT 0xa /* NT Command */
377 #define D_TE 0xb /* TE Command */
378 #define D_CDEC 0xc /* Codec setup */
379 #define D_TEST 0xd /* No comment */
380 #define D_CDM 0xe /* CHI Data mode command */
382 /* Special bits for some commands */
383 #define D_PIPE(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */
385 /* Setup Data Pipe */
387 #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value rcvd */
388 #define D_SDP_CHANGE (2<<18) /* Report any changes */
389 #define D_SDP_EVERY (3<<18) /* Report any changes */
390 #define D_SDP_EOL (1<<17) /* EOL interrupt enable */
391 #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
394 #define D_SDP_MEM (0<<13) /* To/from memory */
395 #define D_SDP_HDLC (2<<13)
396 #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
397 #define D_SDP_SER (4<<13) /* Serial to serial */
398 #define D_SDP_FIXED (6<<13) /* Short only */
399 #define D_SDP_MODE(v) ((v)&(7<<13))
401 #define D_SDP_TO_SER (1<<12) /* Direction */
402 #define D_SDP_FROM_SER (0<<12) /* Direction */
403 #define D_SDP_MSB (1<<11) /* Bit order within Byte */
404 #define D_SDP_LSB (0<<11) /* Bit order within Byte */
405 #define D_SDP_P (1<<10) /* Pointer Valid */
406 #define D_SDP_A (1<<8) /* Abort */
407 #define D_SDP_C (1<<7) /* Clear */
409 /* Define Time Slot */
410 #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
411 #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
412 #define D_DTS_INS (1<<15) /* Insert Time Slot */
413 #define D_DTS_DEL (0<<15) /* Delete Time Slot */
414 #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
415 #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
417 /* Time Slot defines */
418 #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
419 #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
420 #define D_TS_DI (1<<13) /* Data Invert */
421 #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
422 #define D_TS_MONITOR (2<<10) /* Monitor pipe */
423 #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
424 #define D_TS_ANCHOR (7<<10) /* Starting short pipes */
425 #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
426 #define D_TS_NEXT(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */
428 /* Concentration Highway Interface Modes */
429 #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
430 #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
431 #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
432 #define D_CHI_OD (1<<13) /* Open Drain Enable */
433 #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
434 #define D_CHI_FD (1<<11) /* Frame Drive */
435 #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
437 /* NT: These are here for completeness */
438 #define D_NT_FBIT (1<<17) /* Frame Bit */
439 #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
440 #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
441 #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
442 #define D_NT_ISNT (1<<13) /* Configfure interface as NT */
443 #define D_NT_FT (1<<12) /* Fixed Timing */
444 #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
445 #define D_NT_IFA (1<<10) /* Inhibit Final Activation */
446 #define D_NT_ACT (1<<9) /* Activate Interface */
447 #define D_NT_MFE (1<<8) /* Multiframe Enable */
448 #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
449 #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
450 #define D_NT_FACT (1<<1) /* Force Activation */
451 #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
454 #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
455 #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
456 #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
459 #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
460 #define D_TEST_SIZE(v) ((v)<<11) /* */
461 #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
462 #define D_TEST_PROC 0x6 /* MicroProcessor test */
463 #define D_TEST_SER 0x7 /* Serial-Controller test */
464 #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
465 #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
466 #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
467 #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
468 #define D_TEST_DUMP 0xe /* ROM Dump */
471 #define D_CDM_THI (1<<8) /* Transmit Data on CHIDR Pin */
472 #define D_CDM_RHI (1<<7) /* Receive Data on CHIDX Pin */
473 #define D_CDM_RCE (1<<6) /* Receive on Rising Edge of CHICK */
474 #define D_CDM_XCE (1<<2) /* Transmit Data on Rising Edge of CHICK */
475 #define D_CDM_XEN (1<<1) /* Transmit Highway Enable */
476 #define D_CDM_REN (1<<0) /* Receive Highway Enable */
479 #define D_INTR_BRDY 1 /* Buffer Ready for processing */
480 #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
481 #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
482 #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
483 #define D_INTR_EOL 5 /* End of List */
484 #define D_INTR_CMDI 6 /* Command has bean read */
485 #define D_INTR_XCMP 8 /* Transmission of frame complete */
486 #define D_INTR_SBRI 9 /* BRI status change info */
487 #define D_INTR_FXDT 10 /* Fixed data change */
488 #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
489 #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
490 #define D_INTR_DBYT 12 /* Dropped by frame slip */
491 #define D_INTR_RBYT 13 /* Repeated by frame slip */
492 #define D_INTR_LINT 14 /* Lost Interrupt */
493 #define D_INTR_UNDR 15 /* DMA underrun */
497 #define D_INTR_CHI 36
498 #define D_INTR_CMD 38
500 #define D_INTR_GETCHAN(v) (((v)>>24) & 0x3f)
501 #define D_INTR_GETCODE(v) (((v)>>20) & 0xf)
502 #define D_INTR_GETCMD(v) (((v)>>16) & 0xf)
503 #define D_INTR_GETVAL(v) ((v) & 0xffff)
504 #define D_INTR_GETRVAL(v) ((v) & 0xfffff)
506 #define D_P_0 0 /* TE receive anchor */
507 #define D_P_1 1 /* TE transmit anchor */
508 #define D_P_2 2 /* NT transmit anchor */
509 #define D_P_3 3 /* NT receive anchor */
510 #define D_P_4 4 /* CHI send data */
511 #define D_P_5 5 /* CHI receive data */
512 #define D_P_6 6 /* */
513 #define D_P_7 7 /* */
514 #define D_P_8 8 /* */
515 #define D_P_9 9 /* */
516 #define D_P_10 10 /* */
517 #define D_P_11 11 /* */
518 #define D_P_12 12 /* */
519 #define D_P_13 13 /* */
520 #define D_P_14 14 /* */
521 #define D_P_15 15 /* */
522 #define D_P_16 16 /* CHI anchor pipe */
523 #define D_P_17 17 /* CHI send */
524 #define D_P_18 18 /* CHI receive */
525 #define D_P_19 19 /* CHI receive */
526 #define D_P_20 20 /* CHI receive */
527 #define D_P_21 21 /* */
528 #define D_P_22 22 /* */
529 #define D_P_23 23 /* */
530 #define D_P_24 24 /* */
531 #define D_P_25 25 /* */
532 #define D_P_26 26 /* */
533 #define D_P_27 27 /* */
534 #define D_P_28 28 /* */
535 #define D_P_29 29 /* */
536 #define D_P_30 30 /* */
537 #define D_P_31 31 /* */
539 /* Transmit descriptor defines */
540 #define DBRI_TD_F (1<<31) /* End of Frame */
541 #define DBRI_TD_D (1<<30) /* Do not append CRC */
542 #define DBRI_TD_CNT(v) ((v)<<16) /* Number of valid bytes in the buffer */
543 #define DBRI_TD_B (1<<15) /* Final interrupt */
544 #define DBRI_TD_M (1<<14) /* Marker interrupt */
545 #define DBRI_TD_I (1<<13) /* Transmit Idle Characters */
546 #define DBRI_TD_FCNT(v) (v) /* Flag Count */
547 #define DBRI_TD_UNR (1<<3) /* Underrun: transmitter is out of data */
548 #define DBRI_TD_ABT (1<<2) /* Abort: frame aborted */
549 #define DBRI_TD_TBC (1<<0) /* Transmit buffer Complete */
550 #define DBRI_TD_STATUS(v) ((v)&0xff) /* Transmit status */
551 /* Maximum buffer size per TD: almost 8Kb */
552 #define DBRI_TD_MAXCNT ((1 << 13) - 1)
554 /* Receive descriptor defines */
555 #define DBRI_RD_F (1<<31) /* End of Frame */
556 #define DBRI_RD_C (1<<30) /* Completed buffer */
557 #define DBRI_RD_B (1<<15) /* Final interrupt */
558 #define DBRI_RD_M (1<<14) /* Marker interrupt */
559 #define DBRI_RD_BCNT(v) (v) /* Buffer size */
560 #define DBRI_RD_CRC (1<<7) /* 0: CRC is correct */
561 #define DBRI_RD_BBC (1<<6) /* 1: Bad Byte received */
562 #define DBRI_RD_ABT (1<<5) /* Abort: frame aborted */
563 #define DBRI_RD_OVRN (1<<3) /* Overrun: data lost */
564 #define DBRI_RD_STATUS(v) ((v)&0xff) /* Receive status */
565 #define DBRI_RD_CNT(v) (((v)>>16)&0x1fff) /* Valid bytes in the buffer */
567 /* stream_info[] access */
568 /* Translate the ALSA direction into the array index */
569 #define DBRI_STREAMNO(substream) \
570 (substream->stream == \
571 SNDRV_PCM_STREAM_PLAYBACK? DBRI_PLAY: DBRI_REC)
573 /* Return a pointer to dbri_streaminfo */
574 #define DBRI_STREAM(dbri, substream) &dbri->stream_info[DBRI_STREAMNO(substream)]
576 static struct snd_dbri *dbri_list; /* All DBRI devices */
579 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
580 * So we have to reverse the bits. Note: not all bit lengths are supported
582 static __u32 reverse_bytes(__u32 b, int len)
586 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
588 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
590 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
592 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
594 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
599 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
606 ****************************************************************************
607 ************** DBRI initialization and command synchronization *************
608 ****************************************************************************
610 Commands are sent to the DBRI by building a list of them in memory,
611 then writing the address of the first list item to DBRI register 8.
612 The list is terminated with a WAIT command, which generates a
613 CPU interrupt to signal completion.
615 Since the DBRI can run in parallel with the CPU, several means of
616 synchronization present themselves. The method implemented here is close
617 to the original scheme (Rudolf's), and uses 2 counters (wait_send and
618 wait_ackd) to synchronize the command buffer between the CPU and the DBRI.
620 A more sophisticated scheme might involve a circular command buffer
621 or an array of command buffers. A routine could fill one with
622 commands and link it onto a list. When a interrupt signaled
623 completion of the current command buffer, look on the list for
626 Every time a routine wants to write commands to the DBRI, it must
627 first call dbri_cmdlock() and get an initial pointer into dbri->dma->cmd
628 in return. dbri_cmdlock() will block if the previous commands have not
629 been completed yet. After this the commands can be written to the buffer,
630 and dbri_cmdsend() is called with the final pointer value to send them
635 static void dbri_process_interrupt_buffer(struct snd_dbri * dbri);
637 enum dbri_lock { NoGetLock, GetLock };
640 static volatile s32 *dbri_cmdlock(struct snd_dbri * dbri, enum dbri_lock get)
642 int maxloops = MAXLOOPS;
645 if ((get == GetLock) && spin_is_locked(&dbri->lock)) {
646 printk(KERN_ERR "DBRI: cmdlock called while in spinlock.");
650 /* Delay if previous commands are still being processed */
651 while ((--maxloops) > 0 && (dbri->wait_send != dbri->wait_ackd)) {
652 msleep_interruptible(1);
653 /* If dbri_cmdlock() got called from inside the
654 * interrupt handler, this will do the processing.
656 dbri_process_interrupt_buffer(dbri);
659 printk(KERN_ERR "DBRI: Chip never completed command buffer %d\n",
662 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
663 MAXLOOPS - maxloops - 1);
666 /*if (get == GetLock) spin_lock(&dbri->lock); */
667 return &dbri->dma->cmd[0];
670 static void dbri_cmdsend(struct snd_dbri * dbri, volatile s32 * cmd)
674 for (ptr = &dbri->dma->cmd[0]; ptr < cmd; ptr++) {
675 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
678 if ((cmd - &dbri->dma->cmd[0]) >= DBRI_NO_CMDS - 1) {
679 printk(KERN_ERR "DBRI: Command buffer overflow! (bug in driver)\n");
680 /* Ignore the last part. */
681 cmd = &dbri->dma->cmd[DBRI_NO_CMDS - 3];
685 dbri->wait_send &= 0xffff; /* restrict it to a 16 bit counter. */
686 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
687 *(cmd++) = DBRI_CMD(D_WAIT, 1, dbri->wait_send);
689 /* Set command pointer and signal it is valid. */
690 sbus_writel(dbri->dma_dvma, dbri->regs + REG8);
692 /*spin_unlock(&dbri->lock); */
695 /* Lock must be held when calling this */
696 static void dbri_reset(struct snd_dbri * dbri)
700 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
701 sbus_readl(dbri->regs + REG0),
702 sbus_readl(dbri->regs + REG2),
703 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
705 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
706 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
710 /* Lock must not be held before calling this */
711 static void dbri_initialize(struct snd_dbri * dbri)
718 spin_lock_irqsave(&dbri->lock, flags);
722 cmd = dbri_cmdlock(dbri, NoGetLock);
723 dprintk(D_GEN, "init: cmd: %p, int: %p\n",
724 &dbri->dma->cmd[0], &dbri->dma->intr[0]);
726 /* Initialize pipes */
727 for (n = 0; n < DBRI_NO_PIPES; n++)
728 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
730 /* A brute approach - DBRI falls back to working burst size by itself
731 * On SS20 D_S does not work, so do not try so high. */
732 tmp = sbus_readl(dbri->regs + REG0);
735 sbus_writel(tmp, dbri->regs + REG0);
738 * Initialize the interrupt ringbuffer.
740 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
741 dbri->dma->intr[0] = dma_addr;
744 * Set up the interrupt queue
746 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
749 dbri_cmdsend(dbri, cmd);
750 spin_unlock_irqrestore(&dbri->lock, flags);
754 ****************************************************************************
755 ************************** DBRI data pipe management ***********************
756 ****************************************************************************
758 While DBRI control functions use the command and interrupt buffers, the
759 main data path takes the form of data pipes, which can be short (command
760 and interrupt driven), or long (attached to DMA buffers). These functions
761 provide a rudimentary means of setting up and managing the DBRI's pipes,
762 but the calling functions have to make sure they respect the pipes' linked
763 list ordering, among other things. The transmit and receive functions
764 here interface closely with the transmit and receive interrupt code.
767 static int pipe_active(struct snd_dbri * dbri, int pipe)
769 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
772 /* reset_pipe(dbri, pipe)
774 * Called on an in-use pipe to clear anything being transmitted or received
775 * Lock must be held before calling this.
777 static void reset_pipe(struct snd_dbri * dbri, int pipe)
783 if (pipe < 0 || pipe > 31) {
784 printk(KERN_ERR "DBRI: reset_pipe called with illegal pipe number\n");
788 sdp = dbri->pipes[pipe].sdp;
790 printk(KERN_ERR "DBRI: reset_pipe called on uninitialized pipe\n");
794 cmd = dbri_cmdlock(dbri, NoGetLock);
795 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
797 dbri_cmdsend(dbri, cmd);
799 desc = dbri->pipes[pipe].first_desc;
801 dbri->dma->desc[desc].nda = dbri->dma->desc[desc].ba = 0;
802 desc = dbri->next_desc[desc];
805 dbri->pipes[pipe].desc = -1;
806 dbri->pipes[pipe].first_desc = -1;
809 /* FIXME: direction as an argument? */
810 static void setup_pipe(struct snd_dbri * dbri, int pipe, int sdp)
812 if (pipe < 0 || pipe > 31) {
813 printk(KERN_ERR "DBRI: setup_pipe called with illegal pipe number\n");
817 if ((sdp & 0xf800) != sdp) {
818 printk(KERN_ERR "DBRI: setup_pipe called with strange SDP value\n");
822 /* If this is a fixed receive pipe, arrange for an interrupt
823 * every time its data changes
825 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
829 dbri->pipes[pipe].sdp = sdp;
830 dbri->pipes[pipe].desc = -1;
831 dbri->pipes[pipe].first_desc = -1;
833 reset_pipe(dbri, pipe);
836 /* FIXME: direction not needed */
837 static void link_time_slot(struct snd_dbri * dbri, int pipe,
838 enum in_or_out direction, int basepipe,
839 int length, int cycle)
846 if (pipe < 0 || pipe > 31 || basepipe < 0 || basepipe > 31) {
848 "DBRI: link_time_slot called with illegal pipe number\n");
852 if (dbri->pipes[pipe].sdp == 0 || dbri->pipes[basepipe].sdp == 0) {
853 printk(KERN_ERR "DBRI: link_time_slot called on uninitialized pipe\n");
857 /* Deal with CHI special case:
858 * "If transmission on edges 0 or 1 is desired, then cycle n
859 * (where n = # of bit times per frame...) must be used."
860 * - DBRI data sheet, page 11
862 if (basepipe == 16 && direction == PIPEoutput && cycle == 0)
863 cycle = dbri->chi_bpf;
865 if (basepipe == pipe) {
869 /* We're not initializing a new linked list (basepipe != pipe),
870 * so run through the linked list and find where this pipe
871 * should be sloted in, based on its cycle. CHI confuses
872 * things a bit, since it has a single anchor for both its
873 * transmit and receive lists.
875 if (basepipe == 16) {
876 if (direction == PIPEinput) {
877 prevpipe = dbri->chi_in_pipe;
879 prevpipe = dbri->chi_out_pipe;
885 nextpipe = dbri->pipes[prevpipe].nextpipe;
887 while (dbri->pipes[nextpipe].cycle < cycle
888 && dbri->pipes[nextpipe].nextpipe != basepipe) {
890 nextpipe = dbri->pipes[nextpipe].nextpipe;
894 if (prevpipe == 16) {
895 if (direction == PIPEinput) {
896 dbri->chi_in_pipe = pipe;
898 dbri->chi_out_pipe = pipe;
901 dbri->pipes[prevpipe].nextpipe = pipe;
904 dbri->pipes[pipe].nextpipe = nextpipe;
905 dbri->pipes[pipe].cycle = cycle;
906 dbri->pipes[pipe].length = length;
908 cmd = dbri_cmdlock(dbri, NoGetLock);
910 if (direction == PIPEinput) {
911 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
912 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
914 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
917 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
918 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
921 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
924 dbri_cmdsend(dbri, cmd);
927 static void unlink_time_slot(struct snd_dbri * dbri, int pipe,
928 enum in_or_out direction, int prevpipe,
934 if (pipe < 0 || pipe > 31 || prevpipe < 0 || prevpipe > 31) {
936 "DBRI: unlink_time_slot called with illegal pipe number\n");
940 cmd = dbri_cmdlock(dbri, NoGetLock);
942 if (direction == PIPEinput) {
943 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
944 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
945 *(cmd++) = D_TS_NEXT(nextpipe);
948 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
949 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
951 *(cmd++) = D_TS_NEXT(nextpipe);
954 dbri_cmdsend(dbri, cmd);
957 /* xmit_fixed() / recv_fixed()
959 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
960 * expected to change much, and which we don't need to buffer.
961 * The DBRI only interrupts us when the data changes (receive pipes),
962 * or only changes the data when this function is called (transmit pipes).
963 * Only short pipes (numbers 16-31) can be used in fixed data mode.
965 * These function operate on a 32-bit field, no matter how large
966 * the actual time slot is. The interrupt handler takes care of bit
967 * ordering and alignment. An 8-bit time slot will always end up
968 * in the low-order 8 bits, filled either MSB-first or LSB-first,
969 * depending on the settings passed to setup_pipe()
971 static void xmit_fixed(struct snd_dbri * dbri, int pipe, unsigned int data)
975 if (pipe < 16 || pipe > 31) {
976 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
980 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
981 printk(KERN_ERR "DBRI: xmit_fixed: Uninitialized pipe %d\n", pipe);
985 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
986 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
990 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
991 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n", pipe);
995 /* DBRI short pipes always transmit LSB first */
997 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
998 data = reverse_bytes(data, dbri->pipes[pipe].length);
1000 cmd = dbri_cmdlock(dbri, GetLock);
1002 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1005 dbri_cmdsend(dbri, cmd);
1008 static void recv_fixed(struct snd_dbri * dbri, int pipe, volatile __u32 * ptr)
1010 if (pipe < 16 || pipe > 31) {
1011 printk(KERN_ERR "DBRI: recv_fixed called with illegal pipe number\n");
1015 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1016 printk(KERN_ERR "DBRI: recv_fixed called on non-fixed pipe %d\n", pipe);
1020 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1021 printk(KERN_ERR "DBRI: recv_fixed called on transmit pipe %d\n", pipe);
1025 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1030 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1031 * with a DMA buffer.
1033 * Only pipe numbers 0-15 can be used in this mode.
1035 * This function takes a stream number pointing to a data buffer,
1036 * and work by building chains of descriptors which identify the
1037 * data buffers. Buffers too large for a single descriptor will
1038 * be spread across multiple descriptors.
1040 static int setup_descs(struct snd_dbri * dbri, int streamno, unsigned int period)
1042 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1046 int first_desc = -1;
1049 if (info->pipe < 0 || info->pipe > 15) {
1050 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
1054 if (dbri->pipes[info->pipe].sdp == 0) {
1055 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
1060 dvma_buffer = info->dvma_buffer;
1063 if (streamno == DBRI_PLAY) {
1064 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1065 printk(KERN_ERR "DBRI: setup_descs: Called on receive pipe %d\n",
1070 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1072 "DBRI: setup_descs: Called on transmit pipe %d\n",
1076 /* Should be able to queue multiple buffers to receive on a pipe */
1077 if (pipe_active(dbri, info->pipe)) {
1078 printk(KERN_ERR "DBRI: recv_on_pipe: Called on active pipe %d\n",
1083 /* Make sure buffer size is multiple of four */
1090 for (; desc < DBRI_NO_DESCS; desc++) {
1091 if (!dbri->dma->desc[desc].ba)
1094 if (desc == DBRI_NO_DESCS) {
1095 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
1099 if (len > DBRI_TD_MAXCNT) {
1100 mylen = DBRI_TD_MAXCNT; /* 8KB - 1 */
1104 if (mylen > period) {
1108 dbri->next_desc[desc] = -1;
1109 dbri->dma->desc[desc].ba = dvma_buffer;
1110 dbri->dma->desc[desc].nda = 0;
1112 if (streamno == DBRI_PLAY) {
1113 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1114 dbri->dma->desc[desc].word4 = 0;
1115 if (first_desc != -1)
1116 dbri->dma->desc[desc].word1 |= DBRI_TD_M;
1118 dbri->dma->desc[desc].word1 = 0;
1119 dbri->dma->desc[desc].word4 =
1120 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1123 if (first_desc == -1) {
1126 dbri->next_desc[last_desc] = desc;
1127 dbri->dma->desc[last_desc].nda =
1128 dbri->dma_dvma + dbri_dma_off(desc, desc);
1132 dvma_buffer += mylen;
1136 if (first_desc == -1 || last_desc == -1) {
1137 printk(KERN_ERR "DBRI: setup_descs: Not enough descriptors available\n");
1141 dbri->dma->desc[last_desc].word1 &= ~DBRI_TD_M;
1142 if (streamno == DBRI_PLAY) {
1143 dbri->dma->desc[last_desc].word1 |=
1144 DBRI_TD_I | DBRI_TD_F | DBRI_TD_B;
1146 dbri->pipes[info->pipe].first_desc = first_desc;
1147 dbri->pipes[info->pipe].desc = first_desc;
1149 for (desc = first_desc; desc != -1; desc = dbri->next_desc[desc]) {
1150 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1152 dbri->dma->desc[desc].word1,
1153 dbri->dma->desc[desc].ba,
1154 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1160 ****************************************************************************
1161 ************************** DBRI - CHI interface ****************************
1162 ****************************************************************************
1164 The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1165 multiplexed serial interface which the DBRI can operate in either master
1166 (give clock/frame sync) or slave (take clock/frame sync) mode.
1170 enum master_or_slave { CHImaster, CHIslave };
1172 static void reset_chi(struct snd_dbri * dbri, enum master_or_slave master_or_slave,
1177 static int chi_initialized = 0; /* FIXME: mutex? */
1179 if (!chi_initialized) {
1181 cmd = dbri_cmdlock(dbri, GetLock);
1183 /* Set CHI Anchor: Pipe 16 */
1185 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(16) | D_PIPE(16);
1186 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1187 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1190 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(16) | D_PIPE(16);
1191 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1193 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1195 dbri->pipes[16].sdp = 1;
1196 dbri->pipes[16].nextpipe = 16;
1197 dbri->chi_in_pipe = 16;
1198 dbri->chi_out_pipe = 16;
1206 for (pipe = dbri->chi_in_pipe;
1207 pipe != 16; pipe = dbri->pipes[pipe].nextpipe) {
1208 unlink_time_slot(dbri, pipe, PIPEinput,
1209 16, dbri->pipes[pipe].nextpipe);
1211 for (pipe = dbri->chi_out_pipe;
1212 pipe != 16; pipe = dbri->pipes[pipe].nextpipe) {
1213 unlink_time_slot(dbri, pipe, PIPEoutput,
1214 16, dbri->pipes[pipe].nextpipe);
1217 dbri->chi_in_pipe = 16;
1218 dbri->chi_out_pipe = 16;
1220 cmd = dbri_cmdlock(dbri, GetLock);
1223 if (master_or_slave == CHIslave) {
1224 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1226 * CHICM = 0 (slave mode, 8 kHz frame rate)
1227 * IR = give immediate CHI status interrupt
1228 * EN = give CHI status interrupt upon change
1230 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1232 /* Setup DBRI for CHI Master - generate clock, FS
1234 * BPF = bits per 8 kHz frame
1235 * 12.288 MHz / CHICM_divisor = clock rate
1236 * FD = 1 - drive CHIFS on rising edge of CHICK
1238 int clockrate = bits_per_frame * 8;
1239 int divisor = 12288 / clockrate;
1241 if (divisor > 255 || divisor * clockrate != 12288)
1242 printk(KERN_ERR "DBRI: illegal bits_per_frame in setup_chi\n");
1244 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1245 | D_CHI_BPF(bits_per_frame));
1248 dbri->chi_bpf = bits_per_frame;
1252 * RCE = 0 - receive on falling edge of CHICK
1253 * XCE = 1 - transmit on rising edge of CHICK
1254 * XEN = 1 - enable transmitter
1255 * REN = 1 - enable receiver
1258 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1259 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
1261 dbri_cmdsend(dbri, cmd);
1265 ****************************************************************************
1266 *********************** CS4215 audio codec management **********************
1267 ****************************************************************************
1269 In the standard SPARC audio configuration, the CS4215 codec is attached
1270 to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1273 static void cs4215_setup_pipes(struct snd_dbri * dbri)
1277 * Pipe 4: Send timeslots 1-4 (audio data)
1278 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1279 * Pipe 6: Receive timeslots 1-4 (audio data)
1280 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1281 * interrupt, and the rest of the data (slot 5 and 8) is
1282 * not relevant for us (only for doublechecking).
1285 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1286 * Pipe 18: Receive timeslot 1 (clb).
1287 * Pipe 19: Receive timeslot 7 (version).
1290 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1291 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1292 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1293 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1295 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1296 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1297 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1300 static int cs4215_init_data(struct cs4215 *mm)
1303 * No action, memory resetting only.
1305 * Data Time Slot 5-8
1306 * Speaker,Line and Headphone enable. Gain set to the half.
1309 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1310 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1311 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1312 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1315 * Control Time Slot 1-4
1316 * 0: Default I/O voltage scale
1317 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1318 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1321 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1322 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1323 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1328 mm->precision = 8; /* For ULAW */
1334 static void cs4215_setdata(struct snd_dbri * dbri, int muted)
1337 dbri->mm.data[0] |= 63;
1338 dbri->mm.data[1] |= 63;
1339 dbri->mm.data[2] &= ~15;
1340 dbri->mm.data[3] &= ~15;
1342 /* Start by setting the playback attenuation. */
1343 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1344 int left_gain = info->left_gain % 64;
1345 int right_gain = info->right_gain % 64;
1347 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1348 dbri->mm.data[1] &= ~0x3f;
1349 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1350 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1352 /* Now set the recording gain. */
1353 info = &dbri->stream_info[DBRI_REC];
1354 left_gain = info->left_gain % 16;
1355 right_gain = info->right_gain % 16;
1356 dbri->mm.data[2] |= CS4215_LG(left_gain);
1357 dbri->mm.data[3] |= CS4215_RG(right_gain);
1360 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1364 * Set the CS4215 to data mode.
1366 static void cs4215_open(struct snd_dbri * dbri)
1371 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1372 dbri->mm.channels, dbri->mm.precision);
1374 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1375 * to make sure this takes. This avoids clicking noises.
1378 cs4215_setdata(dbri, 1);
1383 * Pipe 4: Send timeslots 1-4 (audio data)
1384 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1385 * Pipe 6: Receive timeslots 1-4 (audio data)
1386 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1387 * interrupt, and the rest of the data (slot 5 and 8) is
1388 * not relevant for us (only for doublechecking).
1390 * Just like in control mode, the time slots are all offset by eight
1391 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1392 * even if it's the CHI master. Don't ask me...
1394 tmp = sbus_readl(dbri->regs + REG0);
1395 tmp &= ~(D_C); /* Disable CHI */
1396 sbus_writel(tmp, dbri->regs + REG0);
1398 /* Switch CS4215 to data mode - set PIO3 to 1 */
1399 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1400 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1402 reset_chi(dbri, CHIslave, 128);
1404 /* Note: this next doesn't work for 8-bit stereo, because the two
1405 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1406 * (See CS4215 datasheet Fig 15)
1408 * DBRI non-contiguous mode would be required to make this work.
1410 data_width = dbri->mm.channels * dbri->mm.precision;
1412 link_time_slot(dbri, 20, PIPEoutput, 16, 32, dbri->mm.offset + 32);
1413 link_time_slot(dbri, 4, PIPEoutput, 16, data_width, dbri->mm.offset);
1414 link_time_slot(dbri, 6, PIPEinput, 16, data_width, dbri->mm.offset);
1415 link_time_slot(dbri, 21, PIPEinput, 16, 16, dbri->mm.offset + 40);
1417 /* FIXME: enable CHI after _setdata? */
1418 tmp = sbus_readl(dbri->regs + REG0);
1419 tmp |= D_C; /* Enable CHI */
1420 sbus_writel(tmp, dbri->regs + REG0);
1422 cs4215_setdata(dbri, 0);
1426 * Send the control information (i.e. audio format)
1428 static int cs4215_setctrl(struct snd_dbri * dbri)
1433 /* FIXME - let the CPU do something useful during these delays */
1435 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1436 * to make sure this takes. This avoids clicking noises.
1438 cs4215_setdata(dbri, 1);
1442 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1443 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1445 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1446 sbus_writel(val, dbri->regs + REG2);
1447 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1450 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1451 * operate as CHI master, supplying clocking and frame synchronization.
1453 * In Data mode, however, the CS4215 must be CHI master to insure
1454 * that its data stream is synchronous with its codec.
1456 * The upshot of all this? We start by putting the DBRI into master
1457 * mode, program the CS4215 in Control mode, then switch the CS4215
1458 * into Data mode and put the DBRI into slave mode. Various timing
1459 * requirements must be observed along the way.
1461 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1462 * others?), the addressing of the CS4215's time slots is
1463 * offset by eight bits, so we add eight to all the "cycle"
1464 * values in the Define Time Slot (DTS) commands. This is
1465 * done in hardware by a TI 248 that delays the DBRI->4215
1466 * frame sync signal by eight clock cycles. Anybody know why?
1468 tmp = sbus_readl(dbri->regs + REG0);
1469 tmp &= ~D_C; /* Disable CHI */
1470 sbus_writel(tmp, dbri->regs + REG0);
1472 reset_chi(dbri, CHImaster, 128);
1476 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1477 * Pipe 18: Receive timeslot 1 (clb).
1478 * Pipe 19: Receive timeslot 7 (version).
1481 link_time_slot(dbri, 17, PIPEoutput, 16, 32, dbri->mm.offset);
1482 link_time_slot(dbri, 18, PIPEinput, 16, 8, dbri->mm.offset);
1483 link_time_slot(dbri, 19, PIPEinput, 16, 8, dbri->mm.offset + 48);
1485 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1486 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1487 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1489 tmp = sbus_readl(dbri->regs + REG0);
1490 tmp |= D_C; /* Enable CHI */
1491 sbus_writel(tmp, dbri->regs + REG0);
1493 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i) {
1494 msleep_interruptible(1);
1497 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1502 /* Disable changes to our copy of the version number, as we are about
1503 * to leave control mode.
1505 recv_fixed(dbri, 19, NULL);
1507 /* Terminate CS4215 control mode - data sheet says
1508 * "Set CLB=1 and send two more frames of valid control info"
1510 dbri->mm.ctrl[0] |= CS4215_CLB;
1511 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1513 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1516 cs4215_setdata(dbri, 0);
1522 * Setup the codec with the sampling rate, audio format and number of
1524 * As part of the process we resend the settings for the data
1525 * timeslots as well.
1527 static int cs4215_prepare(struct snd_dbri * dbri, unsigned int rate,
1528 snd_pcm_format_t format, unsigned int channels)
1533 /* Lookup index for this rate */
1534 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1535 if (CS4215_FREQ[freq_idx].freq == rate)
1538 if (CS4215_FREQ[freq_idx].freq != rate) {
1539 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1544 case SNDRV_PCM_FORMAT_MU_LAW:
1545 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1546 dbri->mm.precision = 8;
1548 case SNDRV_PCM_FORMAT_A_LAW:
1549 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1550 dbri->mm.precision = 8;
1552 case SNDRV_PCM_FORMAT_U8:
1553 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1554 dbri->mm.precision = 8;
1556 case SNDRV_PCM_FORMAT_S16_BE:
1557 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1558 dbri->mm.precision = 16;
1561 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1565 /* Add rate parameters */
1566 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1567 dbri->mm.ctrl[2] = CS4215_XCLK |
1568 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1570 dbri->mm.channels = channels;
1571 /* Stereo bit: 8 bit stereo not working yet. */
1572 if ((channels > 1) && (dbri->mm.precision == 16))
1573 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1575 ret = cs4215_setctrl(dbri);
1577 cs4215_open(dbri); /* set codec to data mode */
1585 static int cs4215_init(struct snd_dbri * dbri)
1587 u32 reg2 = sbus_readl(dbri->regs + REG2);
1588 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1590 /* Look for the cs4215 chips */
1591 if (reg2 & D_PIO2) {
1592 dprintk(D_MM, "Onboard CS4215 detected\n");
1593 dbri->mm.onboard = 1;
1595 if (reg2 & D_PIO0) {
1596 dprintk(D_MM, "Speakerbox detected\n");
1597 dbri->mm.onboard = 0;
1599 if (reg2 & D_PIO2) {
1600 printk(KERN_INFO "DBRI: Using speakerbox / "
1601 "ignoring onboard mmcodec.\n");
1602 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1606 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1607 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1611 cs4215_setup_pipes(dbri);
1613 cs4215_init_data(&dbri->mm);
1615 /* Enable capture of the status & version timeslots. */
1616 recv_fixed(dbri, 18, &dbri->mm.status);
1617 recv_fixed(dbri, 19, &dbri->mm.version);
1619 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1620 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1621 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1625 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1631 ****************************************************************************
1632 *************************** DBRI interrupt handler *************************
1633 ****************************************************************************
1635 The DBRI communicates with the CPU mainly via a circular interrupt
1636 buffer. When an interrupt is signaled, the CPU walks through the
1637 buffer and calls dbri_process_one_interrupt() for each interrupt word.
1638 Complicated interrupts are handled by dedicated functions (which
1639 appear first in this file). Any pending interrupts can be serviced by
1640 calling dbri_process_interrupt_buffer(), which works even if the CPU's
1641 interrupts are disabled. This function is used by dbri_cmdlock()
1642 to make sure we're synced up with the chip before each command sequence,
1643 even if we're running cli'ed.
1649 * Transmit the current TD's for recording/playing, if needed.
1650 * For playback, ALSA has filled the DMA memory with new data (we hope).
1652 static void xmit_descs(unsigned long data)
1654 struct snd_dbri *dbri = (struct snd_dbri *) data;
1655 struct dbri_streaminfo *info;
1657 unsigned long flags;
1661 return; /* Disabled */
1663 /* First check the recording stream for buffer overflow */
1664 info = &dbri->stream_info[DBRI_REC];
1665 spin_lock_irqsave(&dbri->lock, flags);
1667 if ((info->left >= info->size) && (info->pipe >= 0)) {
1668 first_td = dbri->pipes[info->pipe].first_desc;
1670 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1672 /* Stream could be closed by the time we run. */
1677 cmd = dbri_cmdlock(dbri, NoGetLock);
1678 *(cmd++) = DBRI_CMD(D_SDP, 0,
1679 dbri->pipes[info->pipe].sdp
1680 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1681 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
1682 dbri_cmdsend(dbri, cmd);
1684 /* Reset our admin of the pipe & bytes read. */
1685 dbri->pipes[info->pipe].desc = first_td;
1690 spin_unlock_irqrestore(&dbri->lock, flags);
1692 /* Now check the playback stream for buffer underflow */
1693 info = &dbri->stream_info[DBRI_PLAY];
1694 spin_lock_irqsave(&dbri->lock, flags);
1696 if ((info->left <= 0) && (info->pipe >= 0)) {
1697 first_td = dbri->pipes[info->pipe].first_desc;
1699 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1701 /* Stream could be closed by the time we run. */
1703 spin_unlock_irqrestore(&dbri->lock, flags);
1707 cmd = dbri_cmdlock(dbri, NoGetLock);
1708 *(cmd++) = DBRI_CMD(D_SDP, 0,
1709 dbri->pipes[info->pipe].sdp
1710 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1711 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
1712 dbri_cmdsend(dbri, cmd);
1714 /* Reset our admin of the pipe & bytes written. */
1715 dbri->pipes[info->pipe].desc = first_td;
1716 info->left = info->size;
1718 spin_unlock_irqrestore(&dbri->lock, flags);
1721 static DECLARE_TASKLET(xmit_descs_task, xmit_descs, 0);
1723 /* transmission_complete_intr()
1725 * Called by main interrupt handler when DBRI signals transmission complete
1726 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1728 * Walks through the pipe's list of transmit buffer descriptors and marks
1729 * them as available. Stops when the first descriptor is found without
1730 * TBC (Transmit Buffer Complete) set, or we've run through them all.
1732 * The DMA buffers are not released, but re-used. Since the transmit buffer
1733 * descriptors are not clobbered, they can be re-submitted as is. This is
1734 * done by the xmit_descs() tasklet above since that could take longer.
1737 static void transmission_complete_intr(struct snd_dbri * dbri, int pipe)
1739 struct dbri_streaminfo *info;
1744 info = &dbri->stream_info[DBRI_PLAY];
1746 td = dbri->pipes[pipe].desc;
1748 if (td >= DBRI_NO_DESCS) {
1749 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1753 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1754 if (!(status & DBRI_TD_TBC)) {
1758 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1760 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1761 len = DBRI_RD_CNT(dbri->dma->desc[td].word1);
1762 info->offset += len;
1765 /* On the last TD, transmit them all again. */
1766 if (dbri->next_desc[td] == -1) {
1767 if (info->left > 0) {
1769 "%d bytes left after last transfer.\n",
1773 tasklet_schedule(&xmit_descs_task);
1776 td = dbri->next_desc[td];
1777 dbri->pipes[pipe].desc = td;
1781 if (spin_is_locked(&dbri->lock)) {
1782 spin_unlock(&dbri->lock);
1783 snd_pcm_period_elapsed(info->substream);
1784 spin_lock(&dbri->lock);
1786 snd_pcm_period_elapsed(info->substream);
1789 static void reception_complete_intr(struct snd_dbri * dbri, int pipe)
1791 struct dbri_streaminfo *info;
1792 int rd = dbri->pipes[pipe].desc;
1795 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1796 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1800 dbri->dma->desc[rd].ba = 0;
1801 dbri->pipes[pipe].desc = dbri->next_desc[rd];
1802 status = dbri->dma->desc[rd].word1;
1803 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1805 info = &dbri->stream_info[DBRI_REC];
1806 info->offset += DBRI_RD_CNT(status);
1807 info->left += DBRI_RD_CNT(status);
1809 /* FIXME: Check status */
1811 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1812 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1814 /* On the last TD, transmit them all again. */
1815 if (dbri->next_desc[rd] == -1) {
1816 if (info->left > info->size) {
1818 "%d bytes recorded in %d size buffer.\n",
1819 info->left, info->size);
1821 tasklet_schedule(&xmit_descs_task);
1825 if (spin_is_locked(&dbri->lock)) {
1826 spin_unlock(&dbri->lock);
1827 snd_pcm_period_elapsed(info->substream);
1828 spin_lock(&dbri->lock);
1830 snd_pcm_period_elapsed(info->substream);
1833 static void dbri_process_one_interrupt(struct snd_dbri * dbri, int x)
1835 int val = D_INTR_GETVAL(x);
1836 int channel = D_INTR_GETCHAN(x);
1837 int command = D_INTR_GETCMD(x);
1838 int code = D_INTR_GETCODE(x);
1840 int rval = D_INTR_GETRVAL(x);
1843 if (channel == D_INTR_CMD) {
1844 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1845 cmds[command], val);
1847 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1848 channel, code, rval);
1851 if (channel == D_INTR_CMD && command == D_WAIT) {
1852 dbri->wait_ackd = val;
1853 if (dbri->wait_send != val) {
1854 printk(KERN_ERR "Processing wait command %d when %d was send.\n",
1855 val, dbri->wait_send);
1862 reception_complete_intr(dbri, channel);
1866 transmission_complete_intr(dbri, channel);
1869 /* UNDR - Transmission underrun
1870 * resend SDP command with clear pipe bit (C) set
1876 int td = dbri->pipes[pipe].desc;
1878 dbri->dma->desc[td].word4 = 0;
1879 cmd = dbri_cmdlock(dbri, NoGetLock);
1880 *(cmd++) = DBRI_CMD(D_SDP, 0,
1881 dbri->pipes[pipe].sdp
1882 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1883 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1884 dbri_cmdsend(dbri, cmd);
1888 /* FXDT - Fixed data change */
1889 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1890 val = reverse_bytes(val, dbri->pipes[channel].length);
1892 if (dbri->pipes[channel].recv_fixed_ptr)
1893 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1896 if (channel != D_INTR_CMD)
1898 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1902 /* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1903 * buffer until it finds a zero word (indicating nothing more to do
1904 * right now). Non-zero words require processing and are handed off
1905 * to dbri_process_one_interrupt AFTER advancing the pointer. This
1906 * order is important since we might recurse back into this function
1907 * and need to make sure the pointer has been advanced first.
1909 static void dbri_process_interrupt_buffer(struct snd_dbri * dbri)
1913 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1914 dbri->dma->intr[dbri->dbri_irqp] = 0;
1916 if (dbri->dbri_irqp == DBRI_INT_BLK)
1917 dbri->dbri_irqp = 1;
1919 dbri_process_one_interrupt(dbri, x);
1923 static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id,
1924 struct pt_regs *regs)
1926 struct snd_dbri *dbri = dev_id;
1927 static int errcnt = 0;
1932 spin_lock(&dbri->lock);
1935 * Read it, so the interrupt goes away.
1937 x = sbus_readl(dbri->regs + REG1);
1939 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1944 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1948 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1952 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1955 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1957 /* Some of these SBus errors cause the chip's SBus circuitry
1958 * to be disabled, so just re-enable and try to keep going.
1960 * The only one I've seen is MRR, which will be triggered
1961 * if you let a transmit pipe underrun, then try to CDP it.
1963 * If these things persist, we reset the chip.
1965 if ((++errcnt) % 10 == 0) {
1966 dprintk(D_INT, "Interrupt errors exceeded.\n");
1969 tmp = sbus_readl(dbri->regs + REG0);
1971 sbus_writel(tmp, dbri->regs + REG0);
1975 dbri_process_interrupt_buffer(dbri);
1977 /* FIXME: Write 0 into regs to ACK interrupt */
1979 spin_unlock(&dbri->lock);
1984 /****************************************************************************
1986 ****************************************************************************/
1987 static struct snd_pcm_hardware snd_dbri_pcm_hw = {
1988 .info = (SNDRV_PCM_INFO_MMAP |
1989 SNDRV_PCM_INFO_INTERLEAVED |
1990 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1991 SNDRV_PCM_INFO_MMAP_VALID),
1992 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1993 SNDRV_PCM_FMTBIT_A_LAW |
1994 SNDRV_PCM_FMTBIT_U8 |
1995 SNDRV_PCM_FMTBIT_S16_BE,
1996 .rates = SNDRV_PCM_RATE_8000_48000,
2001 .buffer_bytes_max = (64 * 1024),
2002 .period_bytes_min = 1,
2003 .period_bytes_max = DBRI_TD_MAXCNT,
2005 .periods_max = 1024,
2008 static int snd_dbri_open(struct snd_pcm_substream *substream)
2010 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2011 struct snd_pcm_runtime *runtime = substream->runtime;
2012 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2013 unsigned long flags;
2015 dprintk(D_USR, "open audio output.\n");
2016 runtime->hw = snd_dbri_pcm_hw;
2018 spin_lock_irqsave(&dbri->lock, flags);
2019 info->substream = substream;
2022 info->dvma_buffer = 0;
2024 spin_unlock_irqrestore(&dbri->lock, flags);
2031 static int snd_dbri_close(struct snd_pcm_substream *substream)
2033 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2034 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2036 dprintk(D_USR, "close audio output.\n");
2037 info->substream = NULL;
2044 static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2045 struct snd_pcm_hw_params *hw_params)
2047 struct snd_pcm_runtime *runtime = substream->runtime;
2048 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2049 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2053 /* set sampling rate, audio format and number of channels */
2054 ret = cs4215_prepare(dbri, params_rate(hw_params),
2055 params_format(hw_params),
2056 params_channels(hw_params));
2060 if ((ret = snd_pcm_lib_malloc_pages(substream,
2061 params_buffer_bytes(hw_params))) < 0) {
2062 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
2066 /* hw_params can get called multiple times. Only map the DMA once.
2068 if (info->dvma_buffer == 0) {
2069 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2070 direction = SBUS_DMA_TODEVICE;
2072 direction = SBUS_DMA_FROMDEVICE;
2074 info->dvma_buffer = sbus_map_single(dbri->sdev,
2076 params_buffer_bytes(hw_params),
2080 direction = params_buffer_bytes(hw_params);
2081 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2082 direction, info->dvma_buffer);
2086 static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
2088 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2089 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2091 dprintk(D_USR, "hw_free.\n");
2093 /* hw_free can get called multiple times. Only unmap the DMA once.
2095 if (info->dvma_buffer) {
2096 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2097 direction = SBUS_DMA_TODEVICE;
2099 direction = SBUS_DMA_FROMDEVICE;
2101 sbus_unmap_single(dbri->sdev, info->dvma_buffer,
2102 substream->runtime->buffer_size, direction);
2103 info->dvma_buffer = 0;
2107 return snd_pcm_lib_free_pages(substream);
2110 static int snd_dbri_prepare(struct snd_pcm_substream *substream)
2112 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2113 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2114 struct snd_pcm_runtime *runtime = substream->runtime;
2117 info->size = snd_pcm_lib_buffer_bytes(substream);
2118 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2119 info->pipe = 4; /* Send pipe */
2121 info->pipe = 6; /* Receive pipe */
2122 info->left = info->size; /* To trigger submittal */
2125 spin_lock_irq(&dbri->lock);
2127 /* Setup the all the transmit/receive desciptors to cover the
2130 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2131 snd_pcm_lib_period_bytes(substream));
2133 runtime->stop_threshold = DBRI_TD_MAXCNT / runtime->channels;
2135 spin_unlock_irq(&dbri->lock);
2137 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2141 static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
2143 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2144 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2148 case SNDRV_PCM_TRIGGER_START:
2149 dprintk(D_USR, "start audio, period is %d bytes\n",
2150 (int)snd_pcm_lib_period_bytes(substream));
2151 /* Enable & schedule the tasklet that re-submits the TDs. */
2152 xmit_descs_task.data = (unsigned long)dbri;
2153 tasklet_schedule(&xmit_descs_task);
2155 case SNDRV_PCM_TRIGGER_STOP:
2156 dprintk(D_USR, "stop audio.\n");
2157 /* Make the tasklet bail out immediately. */
2158 xmit_descs_task.data = 0;
2159 reset_pipe(dbri, info->pipe);
2168 static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
2170 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2171 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2172 snd_pcm_uframes_t ret;
2174 ret = bytes_to_frames(substream->runtime, info->offset)
2175 % substream->runtime->buffer_size;
2176 dprintk(D_USR, "I/O pointer: %ld frames, %d bytes left.\n",
2181 static struct snd_pcm_ops snd_dbri_ops = {
2182 .open = snd_dbri_open,
2183 .close = snd_dbri_close,
2184 .ioctl = snd_pcm_lib_ioctl,
2185 .hw_params = snd_dbri_hw_params,
2186 .hw_free = snd_dbri_hw_free,
2187 .prepare = snd_dbri_prepare,
2188 .trigger = snd_dbri_trigger,
2189 .pointer = snd_dbri_pointer,
2192 static int __devinit snd_dbri_pcm(struct snd_dbri * dbri)
2194 struct snd_pcm *pcm;
2197 if ((err = snd_pcm_new(dbri->card,
2198 /* ID */ "sun_dbri",
2200 /* playback count */ 1,
2201 /* capture count */ 1, &pcm)) < 0)
2203 snd_assert(pcm != NULL, return -EINVAL);
2205 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2206 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2208 pcm->private_data = dbri;
2209 pcm->info_flags = 0;
2210 strcpy(pcm->name, dbri->card->shortname);
2212 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
2213 SNDRV_DMA_TYPE_CONTINUOUS,
2214 snd_dma_continuous_data(GFP_KERNEL),
2215 64 * 1024, 64 * 1024)) < 0) {
2222 /*****************************************************************************
2224 *****************************************************************************/
2226 static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2227 struct snd_ctl_elem_info *uinfo)
2229 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2231 uinfo->value.integer.min = 0;
2232 if (kcontrol->private_value == DBRI_PLAY) {
2233 uinfo->value.integer.max = DBRI_MAX_VOLUME;
2235 uinfo->value.integer.max = DBRI_MAX_GAIN;
2240 static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2241 struct snd_ctl_elem_value *ucontrol)
2243 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2244 struct dbri_streaminfo *info;
2245 snd_assert(dbri != NULL, return -EINVAL);
2246 info = &dbri->stream_info[kcontrol->private_value];
2247 snd_assert(info != NULL, return -EINVAL);
2249 ucontrol->value.integer.value[0] = info->left_gain;
2250 ucontrol->value.integer.value[1] = info->right_gain;
2254 static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2255 struct snd_ctl_elem_value *ucontrol)
2257 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2258 struct dbri_streaminfo *info = &dbri->stream_info[kcontrol->private_value];
2259 unsigned long flags;
2262 if (info->left_gain != ucontrol->value.integer.value[0]) {
2263 info->left_gain = ucontrol->value.integer.value[0];
2266 if (info->right_gain != ucontrol->value.integer.value[1]) {
2267 info->right_gain = ucontrol->value.integer.value[1];
2271 /* First mute outputs, and wait 1/8000 sec (125 us)
2272 * to make sure this takes. This avoids clicking noises.
2274 spin_lock_irqsave(&dbri->lock, flags);
2276 cs4215_setdata(dbri, 1);
2278 cs4215_setdata(dbri, 0);
2280 spin_unlock_irqrestore(&dbri->lock, flags);
2285 static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2286 struct snd_ctl_elem_info *uinfo)
2288 int mask = (kcontrol->private_value >> 16) & 0xff;
2290 uinfo->type = (mask == 1) ?
2291 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2293 uinfo->value.integer.min = 0;
2294 uinfo->value.integer.max = mask;
2298 static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2299 struct snd_ctl_elem_value *ucontrol)
2301 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2302 int elem = kcontrol->private_value & 0xff;
2303 int shift = (kcontrol->private_value >> 8) & 0xff;
2304 int mask = (kcontrol->private_value >> 16) & 0xff;
2305 int invert = (kcontrol->private_value >> 24) & 1;
2306 snd_assert(dbri != NULL, return -EINVAL);
2309 ucontrol->value.integer.value[0] =
2310 (dbri->mm.data[elem] >> shift) & mask;
2312 ucontrol->value.integer.value[0] =
2313 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2317 ucontrol->value.integer.value[0] =
2318 mask - ucontrol->value.integer.value[0];
2323 static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2324 struct snd_ctl_elem_value *ucontrol)
2326 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2327 unsigned long flags;
2328 int elem = kcontrol->private_value & 0xff;
2329 int shift = (kcontrol->private_value >> 8) & 0xff;
2330 int mask = (kcontrol->private_value >> 16) & 0xff;
2331 int invert = (kcontrol->private_value >> 24) & 1;
2334 snd_assert(dbri != NULL, return -EINVAL);
2336 val = (ucontrol->value.integer.value[0] & mask);
2342 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2343 ~(mask << shift)) | val;
2344 changed = (val != dbri->mm.data[elem]);
2346 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2347 ~(mask << shift)) | val;
2348 changed = (val != dbri->mm.ctrl[elem - 4]);
2351 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2352 "mixer-value=%ld, mm-value=0x%x\n",
2353 mask, changed, ucontrol->value.integer.value[0],
2354 dbri->mm.data[elem & 3]);
2357 /* First mute outputs, and wait 1/8000 sec (125 us)
2358 * to make sure this takes. This avoids clicking noises.
2360 spin_lock_irqsave(&dbri->lock, flags);
2362 cs4215_setdata(dbri, 1);
2364 cs4215_setdata(dbri, 0);
2366 spin_unlock_irqrestore(&dbri->lock, flags);
2371 /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2372 timeslots. Shift is the bit offset in the timeslot, mask defines the
2373 number of bits. invert is a boolean for use with attenuation.
2375 #define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2376 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2377 .info = snd_cs4215_info_single, \
2378 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2379 .private_value = entry | (shift << 8) | (mask << 16) | (invert << 24) },
2381 static struct snd_kcontrol_new dbri_controls[] __devinitdata = {
2383 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2384 .name = "Playback Volume",
2385 .info = snd_cs4215_info_volume,
2386 .get = snd_cs4215_get_volume,
2387 .put = snd_cs4215_put_volume,
2388 .private_value = DBRI_PLAY,
2390 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2391 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2392 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2394 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2395 .name = "Capture Volume",
2396 .info = snd_cs4215_info_volume,
2397 .get = snd_cs4215_get_volume,
2398 .put = snd_cs4215_put_volume,
2399 .private_value = DBRI_REC,
2401 /* FIXME: mic/line switch */
2402 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2403 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2404 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2405 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2408 #define NUM_CS4215_CONTROLS (sizeof(dbri_controls)/sizeof(struct snd_kcontrol_new))
2410 static int __init snd_dbri_mixer(struct snd_dbri * dbri)
2412 struct snd_card *card;
2415 snd_assert(dbri != NULL && dbri->card != NULL, return -EINVAL);
2418 strcpy(card->mixername, card->shortname);
2420 for (idx = 0; idx < NUM_CS4215_CONTROLS; idx++) {
2421 if ((err = snd_ctl_add(card,
2422 snd_ctl_new1(&dbri_controls[idx], dbri))) < 0)
2426 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2427 dbri->stream_info[idx].left_gain = 0;
2428 dbri->stream_info[idx].right_gain = 0;
2434 /****************************************************************************
2436 ****************************************************************************/
2437 static void dbri_regs_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
2439 struct snd_dbri *dbri = entry->private_data;
2441 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2442 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2443 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2444 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2448 static void dbri_debug_read(struct snd_info_entry * entry,
2449 struct snd_info_buffer *buffer)
2451 struct snd_dbri *dbri = entry->private_data;
2453 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2455 for (pipe = 0; pipe < 32; pipe++) {
2456 if (pipe_active(dbri, pipe)) {
2457 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2459 "Pipe %d: %s SDP=0x%x desc=%d, "
2460 "len=%d @ %d next %d\n",
2462 ((pptr->sdp & D_SDP_TO_SER) ? "output" : "input"),
2463 pptr->sdp, pptr->desc,
2464 pptr->length, pptr->cycle, pptr->nextpipe);
2470 void snd_dbri_proc(struct snd_dbri * dbri)
2472 struct snd_info_entry *entry;
2474 if (! snd_card_proc_new(dbri->card, "regs", &entry))
2475 snd_info_set_text_ops(entry, dbri, dbri_regs_read);
2478 if (! snd_card_proc_new(dbri->card, "debug", &entry)) {
2479 snd_info_set_text_ops(entry, dbri, dbri_debug_read);
2480 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */
2486 ****************************************************************************
2487 **************************** Initialization ********************************
2488 ****************************************************************************
2490 static void snd_dbri_free(struct snd_dbri * dbri);
2492 static int __init snd_dbri_create(struct snd_card *card,
2493 struct sbus_dev *sdev,
2494 struct linux_prom_irqs *irq, int dev)
2496 struct snd_dbri *dbri = card->private_data;
2499 spin_lock_init(&dbri->lock);
2502 dbri->irq = irq->pri;
2504 dbri->dma = sbus_alloc_consistent(sdev, sizeof(struct dbri_dma),
2506 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma));
2508 dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n",
2509 dbri->dma, dbri->dma_dvma);
2511 /* Map the registers into memory. */
2512 dbri->regs_size = sdev->reg_addrs[0].reg_size;
2513 dbri->regs = sbus_ioremap(&sdev->resource[0], 0,
2514 dbri->regs_size, "DBRI Registers");
2516 printk(KERN_ERR "DBRI: could not allocate registers\n");
2517 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2518 (void *)dbri->dma, dbri->dma_dvma);
2522 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2523 "DBRI audio", dbri);
2525 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2526 sbus_iounmap(dbri->regs, dbri->regs_size);
2527 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2528 (void *)dbri->dma, dbri->dma_dvma);
2532 /* Do low level initialization of the DBRI and CS4215 chips */
2533 dbri_initialize(dbri);
2534 err = cs4215_init(dbri);
2536 snd_dbri_free(dbri);
2540 dbri->next = dbri_list;
2546 static void snd_dbri_free(struct snd_dbri * dbri)
2548 dprintk(D_GEN, "snd_dbri_free\n");
2552 free_irq(dbri->irq, dbri);
2555 sbus_iounmap(dbri->regs, dbri->regs_size);
2558 sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma),
2559 (void *)dbri->dma, dbri->dma_dvma);
2562 static int __init dbri_attach(int prom_node, struct sbus_dev *sdev)
2564 struct snd_dbri *dbri;
2565 struct linux_prom_irqs irq;
2566 struct resource *rp;
2567 struct snd_card *card;
2571 if (sdev->prom_name[9] < 'e') {
2572 printk(KERN_ERR "DBRI: unsupported chip version %c found.\n",
2573 sdev->prom_name[9]);
2577 if (dev >= SNDRV_CARDS)
2584 err = prom_getproperty(prom_node, "intr", (char *)&irq, sizeof(irq));
2586 printk(KERN_ERR "DBRI-%d: Firmware node lacks IRQ property.\n", dev);
2590 card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2591 sizeof(struct snd_dbri));
2595 strcpy(card->driver, "DBRI");
2596 strcpy(card->shortname, "Sun DBRI");
2597 rp = &sdev->resource[0];
2598 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
2600 rp->flags & 0xffL, (unsigned long long)rp->start, irq.pri);
2602 if ((err = snd_dbri_create(card, sdev, &irq, dev)) < 0) {
2603 snd_card_free(card);
2607 dbri = card->private_data;
2608 if ((err = snd_dbri_pcm(dbri)) < 0)
2611 if ((err = snd_dbri_mixer(dbri)) < 0)
2614 /* /proc file handling */
2615 snd_dbri_proc(dbri);
2617 if ((err = snd_card_register(card)) < 0)
2620 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2622 dbri->irq, sdev->prom_name[9], dbri->mm.version);
2628 snd_dbri_free(dbri);
2629 snd_card_free(card);
2633 /* Probe for the dbri chip and then attach the driver. */
2634 static int __init dbri_init(void)
2636 struct sbus_bus *sbus;
2637 struct sbus_dev *sdev;
2640 /* Probe each SBUS for the DBRI chip(s). */
2641 for_all_sbusdev(sdev, sbus) {
2643 * The version is coded in the last character
2645 if (!strncmp(sdev->prom_name, "SUNW,DBRI", 9)) {
2646 dprintk(D_GEN, "DBRI: Found %s in SBUS slot %d\n",
2647 sdev->prom_name, sdev->slot);
2649 if (dbri_attach(sdev->prom_node, sdev) == 0)
2654 return (found > 0) ? 0 : -EIO;
2657 static void __exit dbri_exit(void)
2659 struct snd_dbri *this = dbri_list;
2661 while (this != NULL) {
2662 struct snd_dbri *next = this->next;
2663 struct snd_card *card = this->card;
2665 snd_dbri_free(this);
2666 snd_card_free(card);
2672 module_init(dbri_init);
2673 module_exit(dbri_exit);