1 /* sound/soc/s3c24xx/s3c2412-i2s.c
3 * ALSA Soc Audio Layer - S3C2412 I2S driver
5 * Copyright (c) 2006 Wolfson Microelectronics PLC.
6 * Graeme Gregory graeme.gregory@wolfsonmicro.com
7 * linux@wolfsonmicro.com
9 * Copyright (c) 2007, 2004-2005 Simtec Electronics
10 * http://armlinux.simtec.co.uk/
11 * Ben Dooks <ben@simtec.co.uk>
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/kernel.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/initval.h>
30 #include <sound/soc.h>
31 #include <asm/hardware.h>
36 #include <asm/plat-s3c24xx/regs-s3c2412-iis.h>
38 #include <asm/arch/regs-gpio.h>
39 #include <asm/arch/audio.h>
40 #include <asm/arch/dma.h>
42 #include "s3c24xx-pcm.h"
43 #include "s3c2412-i2s.h"
45 #define S3C2412_I2S_DEBUG 0
46 #define S3C2412_I2S_DEBUG_CON 0
49 #define DBG(x...) printk(KERN_INFO x)
51 #define DBG(x...) do { } while (0)
54 static struct s3c2410_dma_client s3c2412_dma_client_out = {
55 .name = "I2S PCM Stereo out"
58 static struct s3c2410_dma_client s3c2412_dma_client_in = {
59 .name = "I2S PCM Stereo in"
62 static struct s3c24xx_pcm_dma_params s3c2412_i2s_pcm_stereo_out = {
63 .client = &s3c2412_dma_client_out,
64 .channel = DMACH_I2S_OUT,
65 .dma_addr = S3C2410_PA_IIS + S3C2412_IISTXD,
69 static struct s3c24xx_pcm_dma_params s3c2412_i2s_pcm_stereo_in = {
70 .client = &s3c2412_dma_client_in,
71 .channel = DMACH_I2S_IN,
72 .dma_addr = S3C2410_PA_IIS + S3C2412_IISRXD,
76 struct s3c2412_i2s_info {
84 static struct s3c2412_i2s_info s3c2412_i2s;
86 #define bit_set(v, b) (((v) & (b)) ? 1 : 0)
88 #if S3C2412_I2S_DEBUG_CON
89 static void dbg_showcon(const char *fn, u32 con)
91 printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
92 bit_set(con, S3C2412_IISCON_LRINDEX),
93 bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
94 bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
95 bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
96 bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
98 printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
100 bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
101 bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
102 bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
103 bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
104 printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
105 bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
106 bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
107 bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
110 static inline void dbg_showcon(const char *fn, u32 con)
115 /* Turn on or off the transmission path. */
116 static void s3c2412_snd_txctrl(int on)
118 struct s3c2412_i2s_info *i2s = &s3c2412_i2s;
119 void __iomem *regs = i2s->regs;
122 DBG("%s(%d)\n", __func__, on);
124 fic = readl(regs + S3C2412_IISFIC);
125 con = readl(regs + S3C2412_IISCON);
126 mod = readl(regs + S3C2412_IISMOD);
128 DBG("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
131 con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
132 con &= ~S3C2412_IISCON_TXDMA_PAUSE;
133 con &= ~S3C2412_IISCON_TXCH_PAUSE;
135 switch (mod & S3C2412_IISMOD_MODE_MASK) {
136 case S3C2412_IISMOD_MODE_TXONLY:
137 case S3C2412_IISMOD_MODE_TXRX:
138 /* do nothing, we are in the right mode */
141 case S3C2412_IISMOD_MODE_RXONLY:
142 mod &= ~S3C2412_IISMOD_MODE_MASK;
143 mod |= S3C2412_IISMOD_MODE_TXRX;
147 dev_err(i2s->dev, "TXEN: Invalid MODE in IISMOD\n");
150 writel(con, regs + S3C2412_IISCON);
151 writel(mod, regs + S3C2412_IISMOD);
153 /* Note, we do not have any indication that the FIFO problems
154 * tha the S3C2410/2440 had apply here, so we should be able
155 * to disable the DMA and TX without resetting the FIFOS.
158 con |= S3C2412_IISCON_TXDMA_PAUSE;
159 con |= S3C2412_IISCON_TXCH_PAUSE;
160 con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
162 switch (mod & S3C2412_IISMOD_MODE_MASK) {
163 case S3C2412_IISMOD_MODE_TXRX:
164 mod &= ~S3C2412_IISMOD_MODE_MASK;
165 mod |= S3C2412_IISMOD_MODE_RXONLY;
168 case S3C2412_IISMOD_MODE_TXONLY:
169 mod &= ~S3C2412_IISMOD_MODE_MASK;
170 con &= ~S3C2412_IISCON_IIS_ACTIVE;
174 dev_err(i2s->dev, "TXDIS: Invalid MODE in IISMOD\n");
177 writel(mod, regs + S3C2412_IISMOD);
178 writel(con, regs + S3C2412_IISCON);
181 fic = readl(regs + S3C2412_IISFIC);
182 dbg_showcon(__func__, con);
183 DBG("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
186 static void s3c2412_snd_rxctrl(int on)
188 struct s3c2412_i2s_info *i2s = &s3c2412_i2s;
189 void __iomem *regs = i2s->regs;
192 DBG("%s(%d)\n", __func__, on);
194 fic = readl(regs + S3C2412_IISFIC);
195 con = readl(regs + S3C2412_IISCON);
196 mod = readl(regs + S3C2412_IISMOD);
198 DBG("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
201 con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
202 con &= ~S3C2412_IISCON_RXDMA_PAUSE;
203 con &= ~S3C2412_IISCON_RXCH_PAUSE;
205 switch (mod & S3C2412_IISMOD_MODE_MASK) {
206 case S3C2412_IISMOD_MODE_TXRX:
207 case S3C2412_IISMOD_MODE_RXONLY:
208 /* do nothing, we are in the right mode */
211 case S3C2412_IISMOD_MODE_TXONLY:
212 mod &= ~S3C2412_IISMOD_MODE_MASK;
213 mod |= S3C2412_IISMOD_MODE_TXRX;
217 dev_err(i2s->dev, "RXEN: Invalid MODE in IISMOD\n");
220 writel(mod, regs + S3C2412_IISMOD);
221 writel(con, regs + S3C2412_IISCON);
223 /* See txctrl notes on FIFOs. */
225 con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
226 con |= S3C2412_IISCON_RXDMA_PAUSE;
227 con |= S3C2412_IISCON_RXCH_PAUSE;
229 switch (mod & S3C2412_IISMOD_MODE_MASK) {
230 case S3C2412_IISMOD_MODE_RXONLY:
231 con &= ~S3C2412_IISCON_IIS_ACTIVE;
232 mod &= ~S3C2412_IISMOD_MODE_MASK;
235 case S3C2412_IISMOD_MODE_TXRX:
236 mod &= ~S3C2412_IISMOD_MODE_MASK;
237 mod |= S3C2412_IISMOD_MODE_TXONLY;
241 dev_err(i2s->dev, "RXEN: Invalid MODE in IISMOD\n");
244 writel(con, regs + S3C2412_IISCON);
245 writel(mod, regs + S3C2412_IISMOD);
248 fic = readl(regs + S3C2412_IISFIC);
249 DBG("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
254 * Wait for the LR signal to allow synchronisation to the L/R clock
255 * from the codec. May only be needed for slave mode.
257 static int s3c2412_snd_lrsync(void)
260 unsigned long timeout = jiffies + msecs_to_jiffies(5);
262 DBG("Entered %s\n", __func__);
265 iiscon = readl(s3c2412_i2s.regs + S3C2412_IISCON);
266 if (iiscon & S3C2412_IISCON_LRINDEX)
269 if (timeout < jiffies) {
270 printk(KERN_ERR "%s: timeout\n", __func__);
279 * Check whether CPU is the master or slave
281 static inline int s3c2412_snd_is_clkmaster(void)
283 u32 iismod = readl(s3c2412_i2s.regs + S3C2412_IISMOD);
285 DBG("Entered %s\n", __func__);
287 iismod &= S3C2412_IISMOD_MASTER_MASK;
288 return !(iismod == S3C2412_IISMOD_SLAVE);
292 * Set S3C2412 I2S DAI format
294 static int s3c2412_i2s_set_fmt(struct snd_soc_cpu_dai *cpu_dai,
300 DBG("Entered %s\n", __func__);
302 iismod = readl(s3c2412_i2s.regs + S3C2412_IISMOD);
303 DBG("hw_params r: IISMOD: %x \n", iismod);
305 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
306 case SND_SOC_DAIFMT_CBM_CFM:
307 iismod &= ~S3C2412_IISMOD_MASTER_MASK;
308 iismod |= S3C2412_IISMOD_SLAVE;
310 case SND_SOC_DAIFMT_CBS_CFS:
311 iismod &= ~S3C2412_IISMOD_MASTER_MASK;
312 iismod |= S3C2412_IISMOD_MASTER_INTERNAL;
315 DBG("unknwon master/slave format\n");
319 iismod &= ~S3C2412_IISMOD_SDF_MASK;
321 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
322 case SND_SOC_DAIFMT_RIGHT_J:
323 iismod |= S3C2412_IISMOD_SDF_MSB;
325 case SND_SOC_DAIFMT_LEFT_J:
326 iismod |= S3C2412_IISMOD_SDF_LSB;
328 case SND_SOC_DAIFMT_I2S:
329 iismod |= S3C2412_IISMOD_SDF_IIS;
332 DBG("Unknown data format\n");
336 writel(iismod, s3c2412_i2s.regs + S3C2412_IISMOD);
337 DBG("hw_params w: IISMOD: %x \n", iismod);
341 static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
342 struct snd_pcm_hw_params *params)
344 struct snd_soc_pcm_runtime *rtd = substream->private_data;
347 DBG("Entered %s\n", __func__);
349 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
350 rtd->dai->cpu_dai->dma_data = &s3c2412_i2s_pcm_stereo_out;
352 rtd->dai->cpu_dai->dma_data = &s3c2412_i2s_pcm_stereo_in;
354 /* Working copies of register */
355 iismod = readl(s3c2412_i2s.regs + S3C2412_IISMOD);
356 DBG("%s: r: IISMOD: %x\n", __func__, iismod);
358 switch (params_format(params)) {
359 case SNDRV_PCM_FORMAT_S8:
360 iismod |= S3C2412_IISMOD_8BIT;
362 case SNDRV_PCM_FORMAT_S16_LE:
363 iismod &= ~S3C2412_IISMOD_8BIT;
367 writel(iismod, s3c2412_i2s.regs + S3C2412_IISMOD);
368 DBG("%s: w: IISMOD: %x\n", __func__, iismod);
372 static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
374 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
378 DBG("Entered %s\n", __func__);
381 case SNDRV_PCM_TRIGGER_START:
382 /* On start, ensure that the FIFOs are cleared and reset. */
384 writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
385 s3c2412_i2s.regs + S3C2412_IISFIC);
387 /* clear again, just in case */
388 writel(0x0, s3c2412_i2s.regs + S3C2412_IISFIC);
390 case SNDRV_PCM_TRIGGER_RESUME:
391 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
392 if (!s3c2412_snd_is_clkmaster()) {
393 ret = s3c2412_snd_lrsync();
398 local_irq_save(irqs);
401 s3c2412_snd_rxctrl(1);
403 s3c2412_snd_txctrl(1);
405 local_irq_restore(irqs);
408 case SNDRV_PCM_TRIGGER_STOP:
409 case SNDRV_PCM_TRIGGER_SUSPEND:
410 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
411 local_irq_save(irqs);
414 s3c2412_snd_rxctrl(0);
416 s3c2412_snd_txctrl(0);
418 local_irq_restore(irqs);
429 /* default table of all avaialable root fs divisors */
430 static unsigned int s3c2412_iis_fs[] = { 256, 512, 384, 768, 0 };
432 int s3c2412_iis_calc_rate(struct s3c2412_rate_calc *info,
434 unsigned int rate, struct clk *clk)
436 unsigned long clkrate = clk_get_rate(clk);
442 signed int deviation = 0;
443 unsigned int best_fs = 0;
444 unsigned int best_div = 0;
445 unsigned int best_rate = 0;
446 unsigned int best_deviation = INT_MAX;
450 fstab = s3c2412_iis_fs;
452 for (fs = 0;; fs++) {
453 fsdiv = s3c2412_iis_fs[fs];
458 fsclk = clkrate / fsdiv;
461 if ((fsclk % rate) > (rate / 2))
467 actual = clkrate / (fsdiv * div);
468 deviation = actual - rate;
470 printk(KERN_DEBUG "%dfs: div %d => result %d, deviation %d\n",
471 fsdiv, div, actual, deviation);
473 deviation = abs(deviation);
475 if (deviation < best_deviation) {
479 best_deviation = deviation;
486 printk(KERN_DEBUG "best: fs=%d, div=%d, rate=%d\n",
487 best_fs, best_div, best_rate);
489 info->fs_div = best_fs;
490 info->clk_div = best_div;
494 EXPORT_SYMBOL_GPL(s3c2412_iis_calc_rate);
497 * Set S3C2412 Clock source
499 static int s3c2412_i2s_set_sysclk(struct snd_soc_cpu_dai *cpu_dai,
500 int clk_id, unsigned int freq, int dir)
502 u32 iismod = readl(s3c2412_i2s.regs + S3C2412_IISMOD);
504 DBG("%s(%p, %d, %u, %d)\n", __func__, cpu_dai, clk_id,
508 case S3C2412_CLKSRC_PCLK:
509 iismod &= ~S3C2412_IISMOD_MASTER_MASK;
510 iismod |= S3C2412_IISMOD_MASTER_INTERNAL;
512 case S3C2412_CLKSRC_I2SCLK:
513 iismod &= ~S3C2412_IISMOD_MASTER_MASK;
514 iismod |= S3C2412_IISMOD_MASTER_EXTERNAL;
520 writel(iismod, s3c2412_i2s.regs + S3C2412_IISMOD);
525 * Set S3C2412 Clock dividers
527 static int s3c2412_i2s_set_clkdiv(struct snd_soc_cpu_dai *cpu_dai,
530 struct s3c2412_i2s_info *i2s = &s3c2412_i2s;
533 DBG("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
536 case S3C2412_DIV_BCLK:
537 reg = readl(i2s->regs + S3C2412_IISMOD);
538 reg &= ~S3C2412_IISMOD_BCLK_MASK;
539 writel(reg | div, i2s->regs + S3C2412_IISMOD);
541 DBG("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
544 case S3C2412_DIV_RCLK:
546 /* convert value to bit field */
550 div = S3C2412_IISMOD_RCLK_256FS;
554 div = S3C2412_IISMOD_RCLK_384FS;
558 div = S3C2412_IISMOD_RCLK_512FS;
562 div = S3C2412_IISMOD_RCLK_768FS;
570 reg = readl(s3c2412_i2s.regs + S3C2412_IISMOD);
571 reg &= ~S3C2412_IISMOD_RCLK_MASK;
572 writel(reg | div, i2s->regs + S3C2412_IISMOD);
573 DBG("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
576 case S3C2412_DIV_PRESCALER:
578 writel((div << 8) | S3C2412_IISPSR_PSREN,
579 i2s->regs + S3C2412_IISPSR);
581 writel(0x0, i2s->regs + S3C2412_IISPSR);
583 DBG("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
593 struct clk *s3c2412_get_iisclk(void)
595 return s3c2412_i2s.iis_clk;
597 EXPORT_SYMBOL_GPL(s3c2412_get_iisclk);
600 static int s3c2412_i2s_probe(struct platform_device *pdev)
602 DBG("Entered %s\n", __func__);
604 s3c2412_i2s.dev = &pdev->dev;
606 s3c2412_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
607 if (s3c2412_i2s.regs == NULL)
610 s3c2412_i2s.iis_pclk = clk_get(&pdev->dev, "iis");
611 if (s3c2412_i2s.iis_pclk == NULL) {
612 DBG("failed to get iis_clock\n");
613 iounmap(s3c2412_i2s.regs);
617 s3c2412_i2s.iis_cclk = clk_get(&pdev->dev, "i2sclk");
618 if (s3c2412_i2s.iis_cclk == NULL) {
619 DBG("failed to get i2sclk clock\n");
620 iounmap(s3c2412_i2s.regs);
624 clk_set_parent(s3c2412_i2s.iis_cclk, clk_get(NULL, "mpll"));
626 clk_enable(s3c2412_i2s.iis_pclk);
627 clk_enable(s3c2412_i2s.iis_cclk);
629 s3c2412_i2s.iis_clk = s3c2412_i2s.iis_pclk;
631 /* Configure the I2S pins in correct mode */
632 s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
633 s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
634 s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
635 s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
636 s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
638 s3c2412_snd_txctrl(0);
639 s3c2412_snd_rxctrl(0);
644 #define S3C2412_I2S_RATES \
645 (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
646 SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
647 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
649 struct snd_soc_cpu_dai s3c2412_i2s_dai = {
650 .name = "s3c2412-i2s",
652 .type = SND_SOC_DAI_I2S,
653 .probe = s3c2412_i2s_probe,
657 .rates = S3C2412_I2S_RATES,
658 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
663 .rates = S3C2412_I2S_RATES,
664 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
667 .trigger = s3c2412_i2s_trigger,
668 .hw_params = s3c2412_i2s_hw_params,
671 .set_fmt = s3c2412_i2s_set_fmt,
672 .set_clkdiv = s3c2412_i2s_set_clkdiv,
673 .set_sysclk = s3c2412_i2s_set_sysclk,
676 EXPORT_SYMBOL_GPL(s3c2412_i2s_dai);
678 /* Module information */
679 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
680 MODULE_DESCRIPTION("S3C2412 I2S SoC Interface");
681 MODULE_LICENSE("GPL");