2 * wm9081.c -- WM9081 ALSA SoC Audio driver
6 * Copyright 2009 Wolfson Microelectronics plc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/soc-dapm.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
29 #include <sound/wm9081.h>
32 static u16 wm9081_reg_defaults[] = {
33 0x0000, /* R0 - Software Reset */
35 0x00B9, /* R2 - Analogue Lineout */
36 0x00B9, /* R3 - Analogue Speaker PGA */
37 0x0001, /* R4 - VMID Control */
38 0x0068, /* R5 - Bias Control 1 */
40 0x0000, /* R7 - Analogue Mixer */
41 0x0000, /* R8 - Anti Pop Control */
42 0x01DB, /* R9 - Analogue Speaker 1 */
43 0x0018, /* R10 - Analogue Speaker 2 */
44 0x0180, /* R11 - Power Management */
45 0x0000, /* R12 - Clock Control 1 */
46 0x0038, /* R13 - Clock Control 2 */
47 0x4000, /* R14 - Clock Control 3 */
49 0x0000, /* R16 - FLL Control 1 */
50 0x0200, /* R17 - FLL Control 2 */
51 0x0000, /* R18 - FLL Control 3 */
52 0x0204, /* R19 - FLL Control 4 */
53 0x0000, /* R20 - FLL Control 5 */
55 0x0000, /* R22 - Audio Interface 1 */
56 0x0002, /* R23 - Audio Interface 2 */
57 0x0008, /* R24 - Audio Interface 3 */
58 0x0022, /* R25 - Audio Interface 4 */
59 0x0000, /* R26 - Interrupt Status */
60 0x0006, /* R27 - Interrupt Status Mask */
61 0x0000, /* R28 - Interrupt Polarity */
62 0x0000, /* R29 - Interrupt Control */
63 0x00C0, /* R30 - DAC Digital 1 */
64 0x0008, /* R31 - DAC Digital 2 */
65 0x09AF, /* R32 - DRC 1 */
66 0x4201, /* R33 - DRC 2 */
67 0x0000, /* R34 - DRC 3 */
68 0x0000, /* R35 - DRC 4 */
71 0x0000, /* R38 - Write Sequencer 1 */
72 0x0000, /* R39 - Write Sequencer 2 */
73 0x0002, /* R40 - MW Slave 1 */
75 0x0000, /* R42 - EQ 1 */
76 0x0000, /* R43 - EQ 2 */
77 0x0FCA, /* R44 - EQ 3 */
78 0x0400, /* R45 - EQ 4 */
79 0x00B8, /* R46 - EQ 5 */
80 0x1EB5, /* R47 - EQ 6 */
81 0xF145, /* R48 - EQ 7 */
82 0x0B75, /* R49 - EQ 8 */
83 0x01C5, /* R50 - EQ 9 */
84 0x169E, /* R51 - EQ 10 */
85 0xF829, /* R52 - EQ 11 */
86 0x07AD, /* R53 - EQ 12 */
87 0x1103, /* R54 - EQ 13 */
88 0x1C58, /* R55 - EQ 14 */
89 0xF373, /* R56 - EQ 15 */
90 0x0A54, /* R57 - EQ 16 */
91 0x0558, /* R58 - EQ 17 */
92 0x0564, /* R59 - EQ 18 */
93 0x0559, /* R60 - EQ 19 */
94 0x4000, /* R61 - EQ 20 */
100 } clk_sys_rates[] = {
131 int div; /* *10 due to .5s */
158 struct snd_soc_codec codec;
159 u16 reg_cache[WM9081_MAX_REGISTER + 1];
168 struct wm9081_retune_mobile_config *retune;
171 static int wm9081_volatile_register(unsigned int reg)
174 case WM9081_SOFTWARE_RESET:
181 static int wm9081_reset(struct snd_soc_codec *codec)
183 return snd_soc_write(codec, WM9081_SOFTWARE_RESET, 0);
186 static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
187 static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
188 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
189 static unsigned int drc_max_tlv[] = {
190 TLV_DB_RANGE_HEAD(4),
191 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
192 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
193 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
194 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
196 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
197 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
199 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
201 static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
202 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
203 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
205 static const char *drc_high_text[] = {
214 static const struct soc_enum drc_high =
215 SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text);
217 static const char *drc_low_text[] = {
225 static const struct soc_enum drc_low =
226 SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text);
228 static const char *drc_atk_text[] = {
243 static const struct soc_enum drc_atk =
244 SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text);
246 static const char *drc_dcy_text[] = {
258 static const struct soc_enum drc_dcy =
259 SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text);
261 static const char *drc_qr_dcy_text[] = {
267 static const struct soc_enum drc_qr_dcy =
268 SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text);
270 static const char *dac_deemph_text[] = {
277 static const struct soc_enum dac_deemph =
278 SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text);
280 static const char *speaker_mode_text[] = {
285 static const struct soc_enum speaker_mode =
286 SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text);
288 static int speaker_mode_get(struct snd_kcontrol *kcontrol,
289 struct snd_ctl_elem_value *ucontrol)
291 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
294 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
295 if (reg & WM9081_SPK_MODE)
296 ucontrol->value.integer.value[0] = 1;
298 ucontrol->value.integer.value[0] = 0;
304 * Stop any attempts to change speaker mode while the speaker is enabled.
306 * We also have some special anti-pop controls dependant on speaker
307 * mode which must be changed along with the mode.
309 static int speaker_mode_put(struct snd_kcontrol *kcontrol,
310 struct snd_ctl_elem_value *ucontrol)
312 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
313 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
314 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
316 /* Are we changing anything? */
317 if (ucontrol->value.integer.value[0] ==
318 ((reg2 & WM9081_SPK_MODE) != 0))
321 /* Don't try to change modes while enabled */
322 if (reg_pwr & WM9081_SPK_ENA)
325 if (ucontrol->value.integer.value[0]) {
327 reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
328 reg2 |= WM9081_SPK_MODE;
331 reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
332 reg2 &= ~WM9081_SPK_MODE;
335 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
340 static const struct snd_kcontrol_new wm9081_snd_controls[] = {
341 SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
342 SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
344 SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
346 SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
347 SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
348 SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
350 SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
351 SOC_ENUM("DRC High Slope", drc_high),
352 SOC_ENUM("DRC Low Slope", drc_low),
353 SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
354 SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
355 SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
356 SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
357 SOC_ENUM("DRC Attack", drc_atk),
358 SOC_ENUM("DRC Decay", drc_dcy),
359 SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
360 SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
361 SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
362 SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
364 SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
366 SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
367 SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
368 SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
369 SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
370 SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
372 SOC_ENUM("DAC Deemphasis", dac_deemph),
373 SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
376 static const struct snd_kcontrol_new wm9081_eq_controls[] = {
377 SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
378 SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
379 SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
380 SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
381 SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
384 static const struct snd_kcontrol_new mixer[] = {
385 SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
386 SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
387 SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
390 static int speaker_event(struct snd_soc_dapm_widget *w,
391 struct snd_kcontrol *kcontrol, int event)
393 struct snd_soc_codec *codec = w->codec;
394 unsigned int reg = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
397 case SND_SOC_DAPM_POST_PMU:
398 reg |= WM9081_SPK_ENA;
401 case SND_SOC_DAPM_PRE_PMD:
402 reg &= ~WM9081_SPK_ENA;
406 snd_soc_write(codec, WM9081_POWER_MANAGEMENT, reg);
419 /* The size in bits of the FLL divide multiplied by 10
420 * to allow rounding later */
421 #define FIXED_FLL_SIZE ((1 << 16) * 10)
430 { 64000, 128000, 3, 8 },
431 { 128000, 256000, 2, 4 },
432 { 256000, 1000000, 1, 2 },
433 { 1000000, 13500000, 0, 1 },
436 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
440 unsigned int K, Ndiv, Nmod, target;
444 /* Fref must be <=13.5MHz */
446 while ((Fref / div) > 13500000) {
450 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
455 fll_div->fll_clk_ref_div = div / 2;
457 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
459 /* Apply the division for our remaining calculations */
462 /* Fvco should be 90-100MHz; don't check the upper bound */
465 while (target < 90000000) {
469 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
474 fll_div->fll_outdiv = div;
476 pr_debug("Fvco=%dHz\n", target);
478 /* Find an appropraite FLL_FRATIO and factor it out of the target */
479 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
480 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
481 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
482 target /= fll_fratios[i].ratio;
486 if (i == ARRAY_SIZE(fll_fratios)) {
487 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
491 /* Now, calculate N.K */
492 Ndiv = target / Fref;
495 Nmod = target % Fref;
496 pr_debug("Nmod=%d\n", Nmod);
498 /* Calculate fractional part - scale up so we can round. */
499 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
503 K = Kpart & 0xFFFFFFFF;
508 /* Move down to proper range now rounding is done */
511 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
512 fll_div->n, fll_div->k,
513 fll_div->fll_fratio, fll_div->fll_outdiv,
514 fll_div->fll_clk_ref_div);
519 static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
520 unsigned int Fref, unsigned int Fout)
522 struct wm9081_priv *wm9081 = codec->private_data;
523 u16 reg1, reg4, reg5;
524 struct _fll_div fll_div;
529 if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
532 /* Disable the FLL */
534 dev_dbg(codec->dev, "FLL disabled\n");
535 wm9081->fll_fref = 0;
536 wm9081->fll_fout = 0;
541 ret = fll_factors(&fll_div, Fref, Fout);
545 reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
546 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
549 case WM9081_SYSCLK_FLL_MCLK:
554 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
558 /* Disable CLK_SYS while we reconfigure */
559 clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
560 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
561 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
562 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
564 /* Any FLL configuration change requires that the FLL be
566 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
567 reg1 &= ~WM9081_FLL_ENA;
568 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
570 /* Apply the configuration */
572 reg1 |= WM9081_FLL_FRAC_MASK;
574 reg1 &= ~WM9081_FLL_FRAC_MASK;
575 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
577 snd_soc_write(codec, WM9081_FLL_CONTROL_2,
578 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
579 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
580 snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
582 reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
583 reg4 &= ~WM9081_FLL_N_MASK;
584 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
585 snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
587 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
588 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
589 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
592 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
594 /* Then bring CLK_SYS up again if it was disabled */
595 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
596 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
598 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
600 wm9081->fll_fref = Fref;
601 wm9081->fll_fout = Fout;
606 static int configure_clock(struct snd_soc_codec *codec)
608 struct wm9081_priv *wm9081 = codec->private_data;
609 int new_sysclk, i, target;
615 switch (wm9081->sysclk_source) {
616 case WM9081_SYSCLK_MCLK:
617 if (wm9081->mclk_rate > 12225000) {
619 wm9081->sysclk_rate = wm9081->mclk_rate / 2;
621 wm9081->sysclk_rate = wm9081->mclk_rate;
623 wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0);
626 case WM9081_SYSCLK_FLL_MCLK:
627 /* If we have a sample rate calculate a CLK_SYS that
628 * gives us a suitable DAC configuration, plus BCLK.
629 * Ideally we would check to see if we can clock
630 * directly from MCLK and only use the FLL if this is
631 * not the case, though care must be taken with free
634 if (wm9081->master && wm9081->bclk) {
635 /* Make sure we can generate CLK_SYS and BCLK
636 * and that we've got 3MHz for optimal
638 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
639 target = wm9081->fs * clk_sys_rates[i].ratio;
641 if (target >= wm9081->bclk &&
646 if (i == ARRAY_SIZE(clk_sys_rates))
649 } else if (wm9081->fs) {
650 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
651 new_sysclk = clk_sys_rates[i].ratio
653 if (new_sysclk > 3000000)
657 if (i == ARRAY_SIZE(clk_sys_rates))
661 new_sysclk = 12288000;
664 ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK,
665 wm9081->mclk_rate, new_sysclk);
667 wm9081->sysclk_rate = new_sysclk;
669 /* Switch SYSCLK over to FLL */
672 wm9081->sysclk_rate = wm9081->mclk_rate;
680 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
682 reg |= WM9081_MCLKDIV2;
684 reg &= ~WM9081_MCLKDIV2;
685 snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
687 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
689 reg |= WM9081_CLK_SRC_SEL;
691 reg &= ~WM9081_CLK_SRC_SEL;
692 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
694 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
699 static int clk_sys_event(struct snd_soc_dapm_widget *w,
700 struct snd_kcontrol *kcontrol, int event)
702 struct snd_soc_codec *codec = w->codec;
703 struct wm9081_priv *wm9081 = codec->private_data;
705 /* This should be done on init() for bypass paths */
706 switch (wm9081->sysclk_source) {
707 case WM9081_SYSCLK_MCLK:
708 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
710 case WM9081_SYSCLK_FLL_MCLK:
711 dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
715 dev_err(codec->dev, "System clock not configured\n");
720 case SND_SOC_DAPM_PRE_PMU:
721 configure_clock(codec);
724 case SND_SOC_DAPM_POST_PMD:
725 /* Disable the FLL if it's running */
726 wm9081_set_fll(codec, 0, 0, 0);
733 static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
734 SND_SOC_DAPM_INPUT("IN1"),
735 SND_SOC_DAPM_INPUT("IN2"),
737 SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0),
739 SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
740 mixer, ARRAY_SIZE(mixer)),
742 SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
744 SND_SOC_DAPM_PGA_E("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0,
746 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
748 SND_SOC_DAPM_OUTPUT("LINEOUT"),
749 SND_SOC_DAPM_OUTPUT("SPKN"),
750 SND_SOC_DAPM_OUTPUT("SPKP"),
752 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
753 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
754 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
755 SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
759 static const struct snd_soc_dapm_route audio_paths[] = {
760 { "DAC", NULL, "CLK_SYS" },
761 { "DAC", NULL, "CLK_DSP" },
763 { "Mixer", "IN1 Switch", "IN1" },
764 { "Mixer", "IN2 Switch", "IN2" },
765 { "Mixer", "Playback Switch", "DAC" },
767 { "LINEOUT PGA", NULL, "Mixer" },
768 { "LINEOUT PGA", NULL, "TOCLK" },
769 { "LINEOUT PGA", NULL, "CLK_SYS" },
771 { "LINEOUT", NULL, "LINEOUT PGA" },
773 { "Speaker PGA", NULL, "Mixer" },
774 { "Speaker PGA", NULL, "TOCLK" },
775 { "Speaker PGA", NULL, "CLK_SYS" },
777 { "SPKN", NULL, "Speaker PGA" },
778 { "SPKP", NULL, "Speaker PGA" },
781 static int wm9081_set_bias_level(struct snd_soc_codec *codec,
782 enum snd_soc_bias_level level)
787 case SND_SOC_BIAS_ON:
790 case SND_SOC_BIAS_PREPARE:
792 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
793 reg &= ~WM9081_VMID_SEL_MASK;
795 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
797 /* Normal bias current */
798 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
799 reg &= ~WM9081_STBY_BIAS_ENA;
800 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
803 case SND_SOC_BIAS_STANDBY:
804 /* Initial cold start */
805 if (codec->bias_level == SND_SOC_BIAS_OFF) {
806 /* Disable LINEOUT discharge */
807 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
808 reg &= ~WM9081_LINEOUT_DISCH;
809 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
811 /* Select startup bias source */
812 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
813 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA;
814 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
816 /* VMID 2*4k; Soft VMID ramp enable */
817 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
818 reg |= WM9081_VMID_RAMP | 0x6;
819 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
823 /* Normal bias enable & soft start off */
824 reg |= WM9081_BIAS_ENA;
825 reg &= ~WM9081_VMID_RAMP;
826 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
828 /* Standard bias source */
829 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
830 reg &= ~WM9081_BIAS_SRC;
831 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
835 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
836 reg &= ~WM9081_VMID_SEL_MASK;
838 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
840 /* Standby bias current on */
841 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
842 reg |= WM9081_STBY_BIAS_ENA;
843 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
846 case SND_SOC_BIAS_OFF:
847 /* Startup bias source */
848 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
849 reg |= WM9081_BIAS_SRC;
850 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
852 /* Disable VMID and biases with soft ramping */
853 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
854 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA);
855 reg |= WM9081_VMID_RAMP;
856 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
858 /* Actively discharge LINEOUT */
859 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
860 reg |= WM9081_LINEOUT_DISCH;
861 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
865 codec->bias_level = level;
870 static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
873 struct snd_soc_codec *codec = dai->codec;
874 struct wm9081_priv *wm9081 = codec->private_data;
875 unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
877 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
878 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
880 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
881 case SND_SOC_DAIFMT_CBS_CFS:
884 case SND_SOC_DAIFMT_CBS_CFM:
885 aif2 |= WM9081_LRCLK_DIR;
888 case SND_SOC_DAIFMT_CBM_CFS:
889 aif2 |= WM9081_BCLK_DIR;
892 case SND_SOC_DAIFMT_CBM_CFM:
893 aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
900 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
901 case SND_SOC_DAIFMT_DSP_B:
902 aif2 |= WM9081_AIF_LRCLK_INV;
903 case SND_SOC_DAIFMT_DSP_A:
906 case SND_SOC_DAIFMT_I2S:
909 case SND_SOC_DAIFMT_RIGHT_J:
911 case SND_SOC_DAIFMT_LEFT_J:
918 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
919 case SND_SOC_DAIFMT_DSP_A:
920 case SND_SOC_DAIFMT_DSP_B:
921 /* frame inversion not valid for DSP modes */
922 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
923 case SND_SOC_DAIFMT_NB_NF:
925 case SND_SOC_DAIFMT_IB_NF:
926 aif2 |= WM9081_AIF_BCLK_INV;
933 case SND_SOC_DAIFMT_I2S:
934 case SND_SOC_DAIFMT_RIGHT_J:
935 case SND_SOC_DAIFMT_LEFT_J:
936 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
937 case SND_SOC_DAIFMT_NB_NF:
939 case SND_SOC_DAIFMT_IB_IF:
940 aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
942 case SND_SOC_DAIFMT_IB_NF:
943 aif2 |= WM9081_AIF_BCLK_INV;
945 case SND_SOC_DAIFMT_NB_IF:
946 aif2 |= WM9081_AIF_LRCLK_INV;
956 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
961 static int wm9081_hw_params(struct snd_pcm_substream *substream,
962 struct snd_pcm_hw_params *params,
963 struct snd_soc_dai *dai)
965 struct snd_soc_codec *codec = dai->codec;
966 struct wm9081_priv *wm9081 = codec->private_data;
967 int ret, i, best, best_val, cur_val;
968 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
970 clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
971 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
973 aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
975 aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
976 aif2 &= ~WM9081_AIF_WL_MASK;
978 aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
979 aif3 &= ~WM9081_BCLK_DIV_MASK;
981 aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
982 aif4 &= ~WM9081_LRCLK_RATE_MASK;
984 /* What BCLK do we need? */
985 wm9081->fs = params_rate(params);
986 wm9081->bclk = 2 * wm9081->fs;
987 switch (params_format(params)) {
988 case SNDRV_PCM_FORMAT_S16_LE:
991 case SNDRV_PCM_FORMAT_S20_3LE:
995 case SNDRV_PCM_FORMAT_S24_LE:
999 case SNDRV_PCM_FORMAT_S32_LE:
1007 if (aif1 & WM9081_AIFDAC_TDM_MODE_MASK) {
1008 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
1009 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
1010 wm9081->bclk *= slots;
1013 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1015 ret = configure_clock(codec);
1019 /* Select nearest CLK_SYS_RATE */
1021 best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
1023 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1024 cur_val = abs((wm9081->sysclk_rate /
1025 clk_sys_rates[i].ratio) - wm9081->fs);;
1026 if (cur_val < best_val) {
1031 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1032 clk_sys_rates[best].ratio);
1033 clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
1034 << WM9081_CLK_SYS_RATE_SHIFT);
1038 best_val = abs(wm9081->fs - sample_rates[0].rate);
1039 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1041 cur_val = abs(wm9081->fs - sample_rates[i].rate);
1042 if (cur_val < best_val) {
1047 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1048 sample_rates[best].rate);
1049 clk_ctrl2 |= (sample_rates[best].sample_rate
1050 << WM9081_SAMPLE_RATE_SHIFT);
1055 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1056 cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
1058 if (cur_val < 0) /* Table is sorted */
1060 if (cur_val < best_val) {
1065 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
1066 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1067 bclk_divs[best].div, wm9081->bclk);
1068 aif3 |= bclk_divs[best].bclk_div;
1070 /* LRCLK is a simple fraction of BCLK */
1071 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1072 aif4 |= wm9081->bclk / wm9081->fs;
1074 /* Apply a ReTune Mobile configuration if it's in use */
1075 if (wm9081->retune) {
1076 struct wm9081_retune_mobile_config *retune = wm9081->retune;
1077 struct wm9081_retune_mobile_setting *s;
1081 best_val = abs(retune->configs[0].rate - wm9081->fs);
1082 for (i = 0; i < retune->num_configs; i++) {
1083 cur_val = abs(retune->configs[i].rate - wm9081->fs);
1084 if (cur_val < best_val) {
1089 s = &retune->configs[best];
1091 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1094 /* If the EQ is enabled then disable it while we write out */
1095 eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
1096 if (eq1 & WM9081_EQ_ENA)
1097 snd_soc_write(codec, WM9081_EQ_1, 0);
1099 /* Write out the other values */
1100 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1101 snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
1103 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
1104 snd_soc_write(codec, WM9081_EQ_1, eq1);
1107 snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1108 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1109 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1110 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
1115 static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1117 struct snd_soc_codec *codec = codec_dai->codec;
1120 reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
1123 reg |= WM9081_DAC_MUTE;
1125 reg &= ~WM9081_DAC_MUTE;
1127 snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
1132 static int wm9081_set_sysclk(struct snd_soc_dai *codec_dai,
1133 int clk_id, unsigned int freq, int dir)
1135 struct snd_soc_codec *codec = codec_dai->codec;
1136 struct wm9081_priv *wm9081 = codec->private_data;
1139 case WM9081_SYSCLK_MCLK:
1140 case WM9081_SYSCLK_FLL_MCLK:
1141 wm9081->sysclk_source = clk_id;
1142 wm9081->mclk_rate = freq;
1152 static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1153 unsigned int mask, int slots)
1155 struct snd_soc_codec *codec = dai->codec;
1156 unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
1158 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1160 if (slots < 1 || slots > 4)
1163 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1181 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
1186 #define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1188 #define WM9081_FORMATS \
1189 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1190 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1192 static struct snd_soc_dai_ops wm9081_dai_ops = {
1193 .hw_params = wm9081_hw_params,
1194 .set_sysclk = wm9081_set_sysclk,
1195 .set_fmt = wm9081_set_dai_fmt,
1196 .digital_mute = wm9081_digital_mute,
1197 .set_tdm_slot = wm9081_set_tdm_slot,
1200 /* We report two channels because the CODEC processes a stereo signal, even
1201 * though it is only capable of handling a mono output.
1203 struct snd_soc_dai wm9081_dai = {
1206 .stream_name = "HiFi Playback",
1209 .rates = WM9081_RATES,
1210 .formats = WM9081_FORMATS,
1212 .ops = &wm9081_dai_ops,
1214 EXPORT_SYMBOL_GPL(wm9081_dai);
1217 static struct snd_soc_codec *wm9081_codec;
1219 static int wm9081_probe(struct platform_device *pdev)
1221 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1222 struct snd_soc_codec *codec;
1223 struct wm9081_priv *wm9081;
1226 if (wm9081_codec == NULL) {
1227 dev_err(&pdev->dev, "Codec device not registered\n");
1231 socdev->card->codec = wm9081_codec;
1232 codec = wm9081_codec;
1233 wm9081 = codec->private_data;
1236 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1238 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
1242 snd_soc_add_controls(codec, wm9081_snd_controls,
1243 ARRAY_SIZE(wm9081_snd_controls));
1244 if (!wm9081->retune) {
1246 "No ReTune Mobile data, using normal EQ\n");
1247 snd_soc_add_controls(codec, wm9081_eq_controls,
1248 ARRAY_SIZE(wm9081_eq_controls));
1251 snd_soc_dapm_new_controls(codec, wm9081_dapm_widgets,
1252 ARRAY_SIZE(wm9081_dapm_widgets));
1253 snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
1254 snd_soc_dapm_new_widgets(codec);
1256 ret = snd_soc_init_card(socdev);
1258 dev_err(codec->dev, "failed to register card: %d\n", ret);
1265 snd_soc_free_pcms(socdev);
1266 snd_soc_dapm_free(socdev);
1271 static int wm9081_remove(struct platform_device *pdev)
1273 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1275 snd_soc_free_pcms(socdev);
1276 snd_soc_dapm_free(socdev);
1282 static int wm9081_suspend(struct platform_device *pdev, pm_message_t state)
1284 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1285 struct snd_soc_codec *codec = socdev->card->codec;
1287 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1292 static int wm9081_resume(struct platform_device *pdev)
1294 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1295 struct snd_soc_codec *codec = socdev->card->codec;
1296 u16 *reg_cache = codec->reg_cache;
1299 for (i = 0; i < codec->reg_cache_size; i++) {
1300 if (i == WM9081_SOFTWARE_RESET)
1303 snd_soc_write(codec, i, reg_cache[i]);
1306 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1311 #define wm9081_suspend NULL
1312 #define wm9081_resume NULL
1315 struct snd_soc_codec_device soc_codec_dev_wm9081 = {
1316 .probe = wm9081_probe,
1317 .remove = wm9081_remove,
1318 .suspend = wm9081_suspend,
1319 .resume = wm9081_resume,
1321 EXPORT_SYMBOL_GPL(soc_codec_dev_wm9081);
1323 static int wm9081_register(struct wm9081_priv *wm9081,
1324 enum snd_soc_control_type control)
1326 struct snd_soc_codec *codec = &wm9081->codec;
1331 dev_err(codec->dev, "Another WM9081 is registered\n");
1336 mutex_init(&codec->mutex);
1337 INIT_LIST_HEAD(&codec->dapm_widgets);
1338 INIT_LIST_HEAD(&codec->dapm_paths);
1340 codec->private_data = wm9081;
1341 codec->name = "WM9081";
1342 codec->owner = THIS_MODULE;
1343 codec->dai = &wm9081_dai;
1345 codec->reg_cache_size = ARRAY_SIZE(wm9081->reg_cache);
1346 codec->reg_cache = &wm9081->reg_cache;
1347 codec->bias_level = SND_SOC_BIAS_OFF;
1348 codec->set_bias_level = wm9081_set_bias_level;
1349 codec->volatile_register = wm9081_volatile_register;
1351 memcpy(codec->reg_cache, wm9081_reg_defaults,
1352 sizeof(wm9081_reg_defaults));
1354 ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
1356 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1360 reg = snd_soc_read(codec, WM9081_SOFTWARE_RESET);
1361 if (reg != 0x9081) {
1362 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1367 ret = wm9081_reset(codec);
1369 dev_err(codec->dev, "Failed to issue reset\n");
1373 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1375 /* Enable zero cross by default */
1376 reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT);
1377 snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
1378 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
1379 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1380 reg | WM9081_SPKPGAZC);
1382 wm9081_dai.dev = codec->dev;
1384 wm9081_codec = codec;
1386 ret = snd_soc_register_codec(codec);
1388 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1392 ret = snd_soc_register_dai(&wm9081_dai);
1394 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1395 snd_soc_unregister_codec(codec);
1406 static void wm9081_unregister(struct wm9081_priv *wm9081)
1408 wm9081_set_bias_level(&wm9081->codec, SND_SOC_BIAS_OFF);
1409 snd_soc_unregister_dai(&wm9081_dai);
1410 snd_soc_unregister_codec(&wm9081->codec);
1412 wm9081_codec = NULL;
1415 static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1416 const struct i2c_device_id *id)
1418 struct wm9081_priv *wm9081;
1419 struct snd_soc_codec *codec;
1421 wm9081 = kzalloc(sizeof(struct wm9081_priv), GFP_KERNEL);
1425 codec = &wm9081->codec;
1426 codec->hw_write = (hw_write_t)i2c_master_send;
1427 wm9081->retune = i2c->dev.platform_data;
1429 i2c_set_clientdata(i2c, wm9081);
1430 codec->control_data = i2c;
1432 codec->dev = &i2c->dev;
1434 return wm9081_register(wm9081, SND_SOC_I2C);
1437 static __devexit int wm9081_i2c_remove(struct i2c_client *client)
1439 struct wm9081_priv *wm9081 = i2c_get_clientdata(client);
1440 wm9081_unregister(wm9081);
1445 static int wm9081_i2c_suspend(struct i2c_client *client, pm_message_t msg)
1447 return snd_soc_suspend_device(&client->dev);
1450 static int wm9081_i2c_resume(struct i2c_client *client)
1452 return snd_soc_resume_device(&client->dev);
1455 #define wm9081_i2c_suspend NULL
1456 #define wm9081_i2c_resume NULL
1459 static const struct i2c_device_id wm9081_i2c_id[] = {
1463 MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
1465 static struct i2c_driver wm9081_i2c_driver = {
1468 .owner = THIS_MODULE,
1470 .probe = wm9081_i2c_probe,
1471 .remove = __devexit_p(wm9081_i2c_remove),
1472 .suspend = wm9081_i2c_suspend,
1473 .resume = wm9081_i2c_resume,
1474 .id_table = wm9081_i2c_id,
1477 static int __init wm9081_modinit(void)
1481 ret = i2c_add_driver(&wm9081_i2c_driver);
1483 printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n",
1489 module_init(wm9081_modinit);
1491 static void __exit wm9081_exit(void)
1493 i2c_del_driver(&wm9081_i2c_driver);
1495 module_exit(wm9081_exit);
1498 MODULE_DESCRIPTION("ASoC WM9081 driver");
1499 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1500 MODULE_LICENSE("GPL");