2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@ru.mvista.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_set_endpoint(codec, "MONO_LOUT", 0), etc.
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
40 #include <linux/i2c.h>
41 #include <linux/platform_device.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
49 #include "tlv320aic3x.h"
51 #define AUDIO_NAME "aic3x"
52 #define AIC3X_VERSION "0.2"
54 /* codec private data */
61 * AIC3X register cache
62 * We can't read the AIC3X register space when we are
63 * using 2 wire for device control, so we cache them instead.
64 * There is no point in caching the reset register
66 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
67 0x00, 0x00, 0x00, 0x10, /* 0 */
68 0x04, 0x00, 0x00, 0x00, /* 4 */
69 0x00, 0x00, 0x00, 0x01, /* 8 */
70 0x00, 0x00, 0x00, 0x80, /* 12 */
71 0x80, 0xff, 0xff, 0x78, /* 16 */
72 0x78, 0x78, 0x78, 0x78, /* 20 */
73 0x78, 0x00, 0x00, 0xfe, /* 24 */
74 0x00, 0x00, 0xfe, 0x00, /* 28 */
75 0x18, 0x18, 0x00, 0x00, /* 32 */
76 0x00, 0x00, 0x00, 0x00, /* 36 */
77 0x00, 0x00, 0x00, 0x80, /* 40 */
78 0x80, 0x00, 0x00, 0x00, /* 44 */
79 0x00, 0x00, 0x00, 0x04, /* 48 */
80 0x00, 0x00, 0x00, 0x00, /* 52 */
81 0x00, 0x00, 0x04, 0x00, /* 56 */
82 0x00, 0x00, 0x00, 0x00, /* 60 */
83 0x00, 0x04, 0x00, 0x00, /* 64 */
84 0x00, 0x00, 0x00, 0x00, /* 68 */
85 0x04, 0x00, 0x00, 0x00, /* 72 */
86 0x00, 0x00, 0x00, 0x00, /* 76 */
87 0x00, 0x00, 0x00, 0x00, /* 80 */
88 0x00, 0x00, 0x00, 0x00, /* 84 */
89 0x00, 0x00, 0x00, 0x00, /* 88 */
90 0x00, 0x00, 0x00, 0x00, /* 92 */
91 0x00, 0x00, 0x00, 0x00, /* 96 */
92 0x00, 0x00, 0x02, /* 100 */
96 * read aic3x register cache
98 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
101 u8 *cache = codec->reg_cache;
102 if (reg >= AIC3X_CACHEREGNUM)
108 * write aic3x register cache
110 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
113 u8 *cache = codec->reg_cache;
114 if (reg >= AIC3X_CACHEREGNUM)
120 * write to the aic3x register space
122 static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
128 * D15..D8 aic3x register offset
129 * D7...D0 register data
131 data[0] = reg & 0xff;
132 data[1] = value & 0xff;
134 aic3x_write_reg_cache(codec, data[0], data[1]);
135 if (codec->hw_write(codec->control_data, data, 2) == 2)
141 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
142 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
143 .info = snd_soc_info_volsw, \
144 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
145 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
148 * All input lines are connected when !0xf and disconnected with 0xf bit field,
149 * so we have to use specific dapm_put call for input mixer
151 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
152 struct snd_ctl_elem_value *ucontrol)
154 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
155 int reg = kcontrol->private_value & 0xff;
156 int shift = (kcontrol->private_value >> 8) & 0x0f;
157 int mask = (kcontrol->private_value >> 16) & 0xff;
158 int invert = (kcontrol->private_value >> 24) & 0x01;
159 unsigned short val, val_mask;
161 struct snd_soc_dapm_path *path;
164 val = (ucontrol->value.integer.value[0] & mask);
172 val_mask = mask << shift;
175 mutex_lock(&widget->codec->mutex);
177 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
178 /* find dapm widget path assoc with kcontrol */
179 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
180 if (path->kcontrol != kcontrol)
183 /* found, now check type */
187 path->connect = invert ? 0 : 1;
189 /* old connection must be powered down */
190 path->connect = invert ? 1 : 0;
195 snd_soc_dapm_sync_endpoints(widget->codec);
198 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
200 mutex_unlock(&widget->codec->mutex);
204 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
205 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
206 static const char *aic3x_left_hpcom_mux[] =
207 { "differential of HPLOUT", "constant VCM", "single-ended" };
208 static const char *aic3x_right_hpcom_mux[] =
209 { "differential of HPROUT", "constant VCM", "single-ended",
210 "differential of HPLCOM", "external feedback" };
211 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
215 #define LHPCOM_ENUM 2
216 #define RHPCOM_ENUM 3
217 #define LINE1L_ENUM 4
218 #define LINE1R_ENUM 5
219 #define LINE2L_ENUM 6
220 #define LINE2R_ENUM 7
222 static const struct soc_enum aic3x_enum[] = {
223 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
224 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
225 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
226 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
227 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
228 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
229 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
230 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
233 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
235 SOC_DOUBLE_R("PCM Playback Volume", LDAC_VOL, RDAC_VOL, 0, 0x7f, 1),
237 SOC_DOUBLE_R("Line DAC Playback Volume", DACL1_2_LLOPM_VOL,
238 DACR1_2_RLOPM_VOL, 0, 0x7f, 1),
239 SOC_DOUBLE_R("Line DAC Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
241 SOC_DOUBLE_R("Line PGA Bypass Playback Volume", PGAL_2_LLOPM_VOL,
242 PGAR_2_RLOPM_VOL, 0, 0x7f, 1),
243 SOC_DOUBLE_R("Line Line2 Bypass Playback Volume", LINE2L_2_LLOPM_VOL,
244 LINE2R_2_RLOPM_VOL, 0, 0x7f, 1),
246 SOC_DOUBLE_R("Mono DAC Playback Volume", DACL1_2_MONOLOPM_VOL,
247 DACR1_2_MONOLOPM_VOL, 0, 0x7f, 1),
248 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
249 SOC_DOUBLE_R("Mono PGA Bypass Playback Volume", PGAL_2_MONOLOPM_VOL,
250 PGAR_2_MONOLOPM_VOL, 0, 0x7f, 1),
251 SOC_DOUBLE_R("Mono Line2 Bypass Playback Volume", LINE2L_2_MONOLOPM_VOL,
252 LINE2R_2_MONOLOPM_VOL, 0, 0x7f, 1),
254 SOC_DOUBLE_R("HP DAC Playback Volume", DACL1_2_HPLOUT_VOL,
255 DACR1_2_HPROUT_VOL, 0, 0x7f, 1),
256 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
258 SOC_DOUBLE_R("HP PGA Bypass Playback Volume", PGAL_2_HPLOUT_VOL,
259 PGAR_2_HPROUT_VOL, 0, 0x7f, 1),
260 SOC_DOUBLE_R("HP Line2 Bypass Playback Volume", LINE2L_2_HPLOUT_VOL,
261 LINE2R_2_HPROUT_VOL, 0, 0x7f, 1),
263 SOC_DOUBLE_R("HPCOM DAC Playback Volume", DACL1_2_HPLCOM_VOL,
264 DACR1_2_HPRCOM_VOL, 0, 0x7f, 1),
265 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
267 SOC_DOUBLE_R("HPCOM PGA Bypass Playback Volume", PGAL_2_HPLCOM_VOL,
268 PGAR_2_HPRCOM_VOL, 0, 0x7f, 1),
269 SOC_DOUBLE_R("HPCOM Line2 Bypass Playback Volume", LINE2L_2_HPLCOM_VOL,
270 LINE2R_2_HPRCOM_VOL, 0, 0x7f, 1),
273 * Note: enable Automatic input Gain Controller with care. It can
274 * adjust PGA to max value when ADC is on and will never go back.
276 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
279 SOC_DOUBLE_R("PGA Capture Volume", LADC_VOL, RADC_VOL, 0, 0x7f, 0),
280 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
283 /* add non dapm controls */
284 static int aic3x_add_controls(struct snd_soc_codec *codec)
288 for (i = 0; i < ARRAY_SIZE(aic3x_snd_controls); i++) {
289 err = snd_ctl_add(codec->card,
290 snd_soc_cnew(&aic3x_snd_controls[i],
300 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
301 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
304 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
305 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
308 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
309 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
311 /* Right HPCOM Mux */
312 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
313 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
315 /* Left DAC_L1 Mixer */
316 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
317 SOC_DAPM_SINGLE("Line Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
318 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
319 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
320 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
323 /* Right DAC_R1 Mixer */
324 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
325 SOC_DAPM_SINGLE("Line Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
326 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
327 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
328 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
332 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
333 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
334 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
335 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
338 /* Right PGA Mixer */
339 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
340 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
341 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
342 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
346 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
347 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
349 /* Right Line1 Mux */
350 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
351 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
354 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
355 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
357 /* Right Line2 Mux */
358 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
359 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
361 /* Left PGA Bypass Mixer */
362 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
363 SOC_DAPM_SINGLE("Line Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
364 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
365 SOC_DAPM_SINGLE("HP Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
366 SOC_DAPM_SINGLE("HPCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
369 /* Right PGA Bypass Mixer */
370 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
371 SOC_DAPM_SINGLE("Line Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
372 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
373 SOC_DAPM_SINGLE("HP Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
374 SOC_DAPM_SINGLE("HPCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
377 /* Left Line2 Bypass Mixer */
378 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
379 SOC_DAPM_SINGLE("Line Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
380 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
381 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
382 SOC_DAPM_SINGLE("HPCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
385 /* Right Line2 Bypass Mixer */
386 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
387 SOC_DAPM_SINGLE("Line Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
388 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
389 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
390 SOC_DAPM_SINGLE("HPCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
393 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
394 /* Left DAC to Left Outputs */
395 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
396 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
397 &aic3x_left_dac_mux_controls),
398 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
399 &aic3x_left_dac_mixer_controls[0],
400 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
401 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
402 &aic3x_left_hpcom_mux_controls),
403 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
404 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
405 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
407 /* Right DAC to Right Outputs */
408 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
409 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
410 &aic3x_right_dac_mux_controls),
411 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
412 &aic3x_right_dac_mixer_controls[0],
413 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
414 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
415 &aic3x_right_hpcom_mux_controls),
416 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
417 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
418 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
421 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
423 /* Left Inputs to Left ADC */
424 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
425 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
426 &aic3x_left_pga_mixer_controls[0],
427 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
428 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
429 &aic3x_left_line1_mux_controls),
430 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
431 &aic3x_left_line2_mux_controls),
433 /* Right Inputs to Right ADC */
434 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
435 LINE1R_2_RADC_CTRL, 2, 0),
436 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
437 &aic3x_right_pga_mixer_controls[0],
438 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
439 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
440 &aic3x_right_line1_mux_controls),
441 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
442 &aic3x_right_line2_mux_controls),
445 SND_SOC_DAPM_MICBIAS("Mic Bias 2V", MICBIAS_CTRL, 6, 0),
446 SND_SOC_DAPM_MICBIAS("Mic Bias 2.5V", MICBIAS_CTRL, 7, 0),
447 SND_SOC_DAPM_MICBIAS("Mic Bias AVDD", MICBIAS_CTRL, 6, 0),
448 SND_SOC_DAPM_MICBIAS("Mic Bias AVDD", MICBIAS_CTRL, 7, 0),
450 /* Left PGA to Left Output bypass */
451 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
452 &aic3x_left_pga_bp_mixer_controls[0],
453 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)),
455 /* Right PGA to Right Output bypass */
456 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
457 &aic3x_right_pga_bp_mixer_controls[0],
458 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)),
460 /* Left Line2 to Left Output bypass */
461 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
462 &aic3x_left_line2_bp_mixer_controls[0],
463 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
465 /* Right Line2 to Right Output bypass */
466 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
467 &aic3x_right_line2_bp_mixer_controls[0],
468 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
470 SND_SOC_DAPM_OUTPUT("LLOUT"),
471 SND_SOC_DAPM_OUTPUT("RLOUT"),
472 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
473 SND_SOC_DAPM_OUTPUT("HPLOUT"),
474 SND_SOC_DAPM_OUTPUT("HPROUT"),
475 SND_SOC_DAPM_OUTPUT("HPLCOM"),
476 SND_SOC_DAPM_OUTPUT("HPRCOM"),
478 SND_SOC_DAPM_INPUT("MIC3L"),
479 SND_SOC_DAPM_INPUT("MIC3R"),
480 SND_SOC_DAPM_INPUT("LINE1L"),
481 SND_SOC_DAPM_INPUT("LINE1R"),
482 SND_SOC_DAPM_INPUT("LINE2L"),
483 SND_SOC_DAPM_INPUT("LINE2R"),
486 static const char *intercon[][3] = {
488 {"Left DAC Mux", "DAC_L1", "Left DAC"},
489 {"Left DAC Mux", "DAC_L2", "Left DAC"},
490 {"Left DAC Mux", "DAC_L3", "Left DAC"},
492 {"Left DAC_L1 Mixer", "Line Switch", "Left DAC Mux"},
493 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
494 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
495 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
496 {"Left Line Out", NULL, "Left DAC Mux"},
497 {"Left HP Out", NULL, "Left DAC Mux"},
499 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
500 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
501 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
503 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
504 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
505 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
506 {"Left HP Com", NULL, "Left HPCOM Mux"},
508 {"LLOUT", NULL, "Left Line Out"},
509 {"LLOUT", NULL, "Left Line Out"},
510 {"HPLOUT", NULL, "Left HP Out"},
511 {"HPLCOM", NULL, "Left HP Com"},
514 {"Right DAC Mux", "DAC_R1", "Right DAC"},
515 {"Right DAC Mux", "DAC_R2", "Right DAC"},
516 {"Right DAC Mux", "DAC_R3", "Right DAC"},
518 {"Right DAC_R1 Mixer", "Line Switch", "Right DAC Mux"},
519 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
520 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
521 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
522 {"Right Line Out", NULL, "Right DAC Mux"},
523 {"Right HP Out", NULL, "Right DAC Mux"},
525 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
526 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
527 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
528 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
529 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
531 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
532 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
533 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
534 {"Right HP Com", NULL, "Right HPCOM Mux"},
536 {"RLOUT", NULL, "Right Line Out"},
537 {"RLOUT", NULL, "Right Line Out"},
538 {"HPROUT", NULL, "Right HP Out"},
539 {"HPRCOM", NULL, "Right HP Com"},
542 {"MONO_LOUT", NULL, "Mono Out"},
543 {"MONO_LOUT", NULL, "Mono Out"},
546 {"Left Line1L Mux", "single-ended", "LINE1L"},
547 {"Left Line1L Mux", "differential", "LINE1L"},
549 {"Left Line2L Mux", "single-ended", "LINE2L"},
550 {"Left Line2L Mux", "differential", "LINE2L"},
552 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
553 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
554 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
556 {"Left ADC", NULL, "Left PGA Mixer"},
559 {"Right Line1R Mux", "single-ended", "LINE1R"},
560 {"Right Line1R Mux", "differential", "LINE1R"},
562 {"Right Line2R Mux", "single-ended", "LINE2R"},
563 {"Right Line2R Mux", "differential", "LINE2R"},
565 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
566 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
567 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
569 {"Right ADC", NULL, "Right PGA Mixer"},
571 /* Left PGA Bypass */
572 {"Left PGA Bypass Mixer", "Line Switch", "Left PGA Mixer"},
573 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
574 {"Left PGA Bypass Mixer", "HP Switch", "Left PGA Mixer"},
575 {"Left PGA Bypass Mixer", "HPCOM Switch", "Left PGA Mixer"},
577 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
578 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
579 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
581 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
582 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
583 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
585 /* Right PGA Bypass */
586 {"Right PGA Bypass Mixer", "Line Switch", "Right PGA Mixer"},
587 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
588 {"Right PGA Bypass Mixer", "HP Switch", "Right PGA Mixer"},
589 {"Right PGA Bypass Mixer", "HPCOM Switch", "Right PGA Mixer"},
591 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
592 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
593 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
594 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
595 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
597 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
598 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
599 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
601 /* Left Line2 Bypass */
602 {"Left Line2 Bypass Mixer", "Line Switch", "Left Line2L Mux"},
603 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
604 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
605 {"Left Line2 Bypass Mixer", "HPCOM Switch", "Left Line2L Mux"},
607 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
608 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
609 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
611 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
612 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
613 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
615 /* Right Line2 Bypass */
616 {"Right Line2 Bypass Mixer", "Line Switch", "Right Line2R Mux"},
617 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
618 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
619 {"Right Line2 Bypass Mixer", "HPCOM Switch", "Right Line2R Mux"},
621 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
622 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
623 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
624 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
625 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
627 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
628 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
629 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
635 static int aic3x_add_widgets(struct snd_soc_codec *codec)
639 for (i = 0; i < ARRAY_SIZE(aic3x_dapm_widgets); i++)
640 snd_soc_dapm_new_control(codec, &aic3x_dapm_widgets[i]);
642 /* set up audio path interconnects */
643 for (i = 0; intercon[i][0] != NULL; i++)
644 snd_soc_dapm_connect_input(codec, intercon[i][0],
645 intercon[i][1], intercon[i][2]);
647 snd_soc_dapm_new_widgets(codec);
651 static int aic3x_hw_params(struct snd_pcm_substream *substream,
652 struct snd_pcm_hw_params *params)
654 struct snd_soc_pcm_runtime *rtd = substream->private_data;
655 struct snd_soc_device *socdev = rtd->socdev;
656 struct snd_soc_codec *codec = socdev->codec;
657 struct aic3x_priv *aic3x = codec->private_data;
658 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
659 u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
662 /* select data word length */
664 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
665 switch (params_format(params)) {
666 case SNDRV_PCM_FORMAT_S16_LE:
668 case SNDRV_PCM_FORMAT_S20_3LE:
671 case SNDRV_PCM_FORMAT_S24_LE:
674 case SNDRV_PCM_FORMAT_S32_LE:
678 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
680 /* Fsref can be 44100 or 48000 */
681 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
683 /* Try to find a value for Q which allows us to bypass the PLL and
684 * generate CODEC_CLK directly. */
685 for (pll_q = 2; pll_q < 18; pll_q++)
686 if (aic3x->sysclk / (128 * pll_q) == fsref) {
693 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
694 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
696 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
698 /* Route Left DAC to left channel input and
699 * right DAC to right channel input */
700 data = (LDAC2LCH | RDAC2RCH);
701 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
702 if (params_rate(params) >= 64000)
703 data |= DUAL_RATE_MODE;
704 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
706 /* codec sample rate select */
707 data = (fsref * 20) / params_rate(params);
708 if (params_rate(params) < 64000)
713 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
719 * find an apropriate setup for j, d, r and p by iterating over
720 * p and r - j and d are calculated for each fraction.
721 * Up to 128 values are probed, the closest one wins the game.
722 * The sysclk is divided by 1000 to prevent integer overflows.
724 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
726 for (r = 1; r <= 16; r++)
727 for (p = 1; p <= 8; p++) {
728 int clk, tmp = (codec_clk * pll_r * 10) / pll_p;
735 if (d != 0 && aic3x->sysclk < 10000000)
738 /* This is actually 1000 * ((j + (d/10000)) * r) / p
739 * The term had to be converted to get rid of the
740 * division by 10000 */
741 clk = ((10000 * j * r) + (d * r)) / (10 * p);
743 /* check whether this values get closer than the best
744 * ones we had before */
745 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
746 pll_j = j; pll_d = d; pll_r = r; pll_p = p;
750 /* Early exit for exact matches */
751 if (clk == codec_clk)
756 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
760 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
761 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
762 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
763 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
764 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
765 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
766 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
771 static int aic3x_mute(struct snd_soc_codec_dai *dai, int mute)
773 struct snd_soc_codec *codec = dai->codec;
774 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
775 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
778 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
779 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
781 aic3x_write(codec, LDAC_VOL, ldac_reg);
782 aic3x_write(codec, RDAC_VOL, rdac_reg);
788 static int aic3x_set_dai_sysclk(struct snd_soc_codec_dai *codec_dai,
789 int clk_id, unsigned int freq, int dir)
791 struct snd_soc_codec *codec = codec_dai->codec;
792 struct aic3x_priv *aic3x = codec->private_data;
794 aic3x->sysclk = freq;
798 static int aic3x_set_dai_fmt(struct snd_soc_codec_dai *codec_dai,
801 struct snd_soc_codec *codec = codec_dai->codec;
802 struct aic3x_priv *aic3x = codec->private_data;
806 /* set master/slave audio interface */
807 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
808 case SND_SOC_DAIFMT_CBM_CFM:
810 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
812 case SND_SOC_DAIFMT_CBS_CFS:
819 /* interface format */
820 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
821 case SND_SOC_DAIFMT_I2S:
823 case SND_SOC_DAIFMT_DSP_A:
824 iface_breg |= (0x01 << 6);
826 case SND_SOC_DAIFMT_RIGHT_J:
827 iface_breg |= (0x02 << 6);
829 case SND_SOC_DAIFMT_LEFT_J:
830 iface_breg |= (0x03 << 6);
837 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
838 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
843 static int aic3x_dapm_event(struct snd_soc_codec *codec, int event)
845 struct aic3x_priv *aic3x = codec->private_data;
849 case SNDRV_CTL_POWER_D0:
850 /* all power is driven by DAPM system */
853 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
854 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
858 case SNDRV_CTL_POWER_D1:
859 case SNDRV_CTL_POWER_D2:
861 case SNDRV_CTL_POWER_D3hot:
863 * all power is driven by DAPM system,
864 * so output power is safe if bypass was set
868 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
869 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
873 case SNDRV_CTL_POWER_D3cold:
874 /* force all power off */
875 reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL);
876 aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON);
877 reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL);
878 aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON);
880 reg = aic3x_read_reg_cache(codec, DAC_PWR);
881 aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON));
883 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
884 aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON);
885 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
886 aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON);
888 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
889 aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON);
890 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
891 aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON);
893 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
894 aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON);
896 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
897 aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON);
898 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
899 aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON);
903 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
904 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
909 codec->dapm_state = event;
914 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
915 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
916 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
918 struct snd_soc_codec_dai aic3x_dai = {
921 .stream_name = "Playback",
924 .rates = AIC3X_RATES,
925 .formats = AIC3X_FORMATS,},
927 .stream_name = "Capture",
930 .rates = AIC3X_RATES,
931 .formats = AIC3X_FORMATS,},
933 .hw_params = aic3x_hw_params,
936 .digital_mute = aic3x_mute,
937 .set_sysclk = aic3x_set_dai_sysclk,
938 .set_fmt = aic3x_set_dai_fmt,
941 EXPORT_SYMBOL_GPL(aic3x_dai);
943 static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
945 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
946 struct snd_soc_codec *codec = socdev->codec;
948 aic3x_dapm_event(codec, SNDRV_CTL_POWER_D3cold);
953 static int aic3x_resume(struct platform_device *pdev)
955 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
956 struct snd_soc_codec *codec = socdev->codec;
959 u8 *cache = codec->reg_cache;
961 /* Sync reg_cache with the hardware */
962 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
965 codec->hw_write(codec->control_data, data, 2);
968 aic3x_dapm_event(codec, codec->suspend_dapm_state);
974 * initialise the AIC3X driver
975 * register the mixer and dsp interfaces with the kernel
977 static int aic3x_init(struct snd_soc_device *socdev)
979 struct snd_soc_codec *codec = socdev->codec;
982 codec->name = "aic3x";
983 codec->owner = THIS_MODULE;
984 codec->read = aic3x_read_reg_cache;
985 codec->write = aic3x_write;
986 codec->dapm_event = aic3x_dapm_event;
987 codec->dai = &aic3x_dai;
989 codec->reg_cache_size = sizeof(aic3x_reg);
990 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
991 if (codec->reg_cache == NULL)
994 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
995 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
998 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1000 printk(KERN_ERR "aic3x: failed to create pcms\n");
1004 /* DAC default volume and mute */
1005 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1006 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1008 /* DAC to HP default volume and route to Output mixer */
1009 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1010 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1011 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1012 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1013 /* DAC to Line Out default volume and route to Output mixer */
1014 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1015 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1016 /* DAC to Mono Line Out default volume and route to Output mixer */
1017 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1018 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1020 /* unmute all outputs */
1021 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1022 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1023 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1024 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1025 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1026 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1027 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1028 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1029 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1030 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1031 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1032 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1033 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1034 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1036 /* ADC default volume and unmute */
1037 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1038 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1039 /* By default route Line1 to ADC PGA mixer */
1040 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1041 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1043 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1044 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1045 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1046 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1047 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1048 /* PGA to Line Out default volume, disconnect from Output Mixer */
1049 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1050 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1051 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1052 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1053 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1055 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1056 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1057 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1058 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1059 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1060 /* Line2 Line Out default volume, disconnect from Output Mixer */
1061 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1062 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1063 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1064 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1065 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1067 /* off, with power on */
1068 aic3x_dapm_event(codec, SNDRV_CTL_POWER_D3hot);
1070 aic3x_add_controls(codec);
1071 aic3x_add_widgets(codec);
1072 ret = snd_soc_register_card(socdev);
1074 printk(KERN_ERR "aic3x: failed to register card\n");
1081 snd_soc_free_pcms(socdev);
1082 snd_soc_dapm_free(socdev);
1084 kfree(codec->reg_cache);
1088 static struct snd_soc_device *aic3x_socdev;
1090 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1092 * AIC3X 2 wire address can be up to 4 devices with device addresses
1093 * 0x18, 0x19, 0x1A, 0x1B
1095 static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END };
1097 /* Magic definition of all other variables and things */
1100 static struct i2c_driver aic3x_i2c_driver;
1101 static struct i2c_client client_template;
1104 * If the i2c layer weren't so broken, we could pass this kind of data
1107 static int aic3x_codec_probe(struct i2c_adapter *adap, int addr, int kind)
1109 struct snd_soc_device *socdev = aic3x_socdev;
1110 struct aic3x_setup_data *setup = socdev->codec_data;
1111 struct snd_soc_codec *codec = socdev->codec;
1112 struct i2c_client *i2c;
1115 if (addr != setup->i2c_address)
1118 client_template.adapter = adap;
1119 client_template.addr = addr;
1121 i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL);
1126 i2c_set_clientdata(i2c, codec);
1127 codec->control_data = i2c;
1129 ret = i2c_attach_client(i2c);
1131 printk(KERN_ERR "aic3x: failed to attach codec at addr %x\n",
1136 ret = aic3x_init(socdev);
1138 printk(KERN_ERR "aic3x: failed to initialise AIC3X\n");
1149 static int aic3x_i2c_detach(struct i2c_client *client)
1151 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1152 i2c_detach_client(client);
1153 kfree(codec->reg_cache);
1158 static int aic3x_i2c_attach(struct i2c_adapter *adap)
1160 return i2c_probe(adap, &addr_data, aic3x_codec_probe);
1163 /* machine i2c codec control layer */
1164 static struct i2c_driver aic3x_i2c_driver = {
1166 .name = "aic3x I2C Codec",
1167 .owner = THIS_MODULE,
1169 .attach_adapter = aic3x_i2c_attach,
1170 .detach_client = aic3x_i2c_detach,
1173 static struct i2c_client client_template = {
1175 .driver = &aic3x_i2c_driver,
1179 static int aic3x_probe(struct platform_device *pdev)
1181 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1182 struct aic3x_setup_data *setup;
1183 struct snd_soc_codec *codec;
1184 struct aic3x_priv *aic3x;
1187 printk(KERN_INFO "AIC3X Audio Codec %s\n", AIC3X_VERSION);
1189 setup = socdev->codec_data;
1190 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1194 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1195 if (aic3x == NULL) {
1200 codec->private_data = aic3x;
1201 socdev->codec = codec;
1202 mutex_init(&codec->mutex);
1203 INIT_LIST_HEAD(&codec->dapm_widgets);
1204 INIT_LIST_HEAD(&codec->dapm_paths);
1206 aic3x_socdev = socdev;
1207 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1208 if (setup->i2c_address) {
1209 normal_i2c[0] = setup->i2c_address;
1210 codec->hw_write = (hw_write_t) i2c_master_send;
1211 ret = i2c_add_driver(&aic3x_i2c_driver);
1213 printk(KERN_ERR "can't add i2c driver");
1216 /* Add other interfaces here */
1221 static int aic3x_remove(struct platform_device *pdev)
1223 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1224 struct snd_soc_codec *codec = socdev->codec;
1226 /* power down chip */
1227 if (codec->control_data)
1228 aic3x_dapm_event(codec, SNDRV_CTL_POWER_D3);
1230 snd_soc_free_pcms(socdev);
1231 snd_soc_dapm_free(socdev);
1232 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1233 i2c_del_driver(&aic3x_i2c_driver);
1235 kfree(codec->private_data);
1241 struct snd_soc_codec_device soc_codec_dev_aic3x = {
1242 .probe = aic3x_probe,
1243 .remove = aic3x_remove,
1244 .suspend = aic3x_suspend,
1245 .resume = aic3x_resume,
1247 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
1249 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1250 MODULE_AUTHOR("Vladimir Barinov");
1251 MODULE_LICENSE("GPL");