SAFE public projects git trees. - safe/jmp/linux-2.6/blob - sound/pci/rme96.c

   1 /*
   2  *   ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
   3  *   interfaces
   4  *
   5  *      Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
   6  *
   7  *      Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
   8  *      code.
   9  *
  10  *   This program is free software; you can redistribute it and/or modify
  11  *   it under the terms of the GNU General Public License as published by
  12  *   the Free Software Foundation; either version 2 of the License, or
  13  *   (at your option) any later version.
  14  *
  15  *   This program is distributed in the hope that it will be useful,
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *   GNU General Public License for more details.
  19  *
  20  *   You should have received a copy of the GNU General Public License
  21  *   along with this program; if not, write to the Free Software
  22  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  *
  24  */
  25
  26 #include <sound/driver.h>
  27 #include <linux/delay.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/pci.h>
  31 #include <linux/slab.h>
  32 #include <linux/moduleparam.h>
  33
  34 #include <sound/core.h>
  35 #include <sound/info.h>
  36 #include <sound/control.h>
  37 #include <sound/pcm.h>
  38 #include <sound/pcm_params.h>
  39 #include <sound/asoundef.h>
  40 #include <sound/initval.h>
  41
  42 #include <asm/io.h>
  43
  44 /* note, two last pcis should be equal, it is not a bug */
  45
  46 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
  47 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
  48                    "Digi96/8 PAD");
  49 MODULE_LICENSE("GPL");
  50 MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
  51                 "{RME,Digi96/8},"
  52                 "{RME,Digi96/8 PRO},"
  53                 "{RME,Digi96/8 PST},"
  54                 "{RME,Digi96/8 PAD}}");
  55
  56 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  57 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  58 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  59
  60 module_param_array(index, int, NULL, 0444);
  61 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
  62 module_param_array(id, charp, NULL, 0444);
  63 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
  64 module_param_array(enable, bool, NULL, 0444);
  65 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
  66
  67 /*
  68  * Defines for RME Digi96 series, from internal RME reference documents
  69  * dated 12.01.00
  70  */
  71
  72 #define RME96_SPDIF_NCHANNELS 2
  73
  74 /* Playback and capture buffer size */
  75 #define RME96_BUFFER_SIZE 0x10000
  76
  77 /* IO area size */
  78 #define RME96_IO_SIZE 0x60000
  79
  80 /* IO area offsets */
  81 #define RME96_IO_PLAY_BUFFER      0x0
  82 #define RME96_IO_REC_BUFFER       0x10000
  83 #define RME96_IO_CONTROL_REGISTER 0x20000
  84 #define RME96_IO_ADDITIONAL_REG   0x20004
  85 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
  86 #define RME96_IO_CONFIRM_REC_IRQ  0x2000C
  87 #define RME96_IO_SET_PLAY_POS     0x40000
  88 #define RME96_IO_RESET_PLAY_POS   0x4FFFC
  89 #define RME96_IO_SET_REC_POS      0x50000
  90 #define RME96_IO_RESET_REC_POS    0x5FFFC
  91 #define RME96_IO_GET_PLAY_POS     0x20000
  92 #define RME96_IO_GET_REC_POS      0x30000
  93
  94 /* Write control register bits */
  95 #define RME96_WCR_START     (1 << 0)
  96 #define RME96_WCR_START_2   (1 << 1)
  97 #define RME96_WCR_GAIN_0    (1 << 2)
  98 #define RME96_WCR_GAIN_1    (1 << 3)
  99 #define RME96_WCR_MODE24    (1 << 4)
 100 #define RME96_WCR_MODE24_2  (1 << 5)
 101 #define RME96_WCR_BM        (1 << 6)
 102 #define RME96_WCR_BM_2      (1 << 7)
 103 #define RME96_WCR_ADAT      (1 << 8)
 104 #define RME96_WCR_FREQ_0    (1 << 9)
 105 #define RME96_WCR_FREQ_1    (1 << 10)
 106 #define RME96_WCR_DS        (1 << 11)
 107 #define RME96_WCR_PRO       (1 << 12)
 108 #define RME96_WCR_EMP       (1 << 13)
 109 #define RME96_WCR_SEL       (1 << 14)
 110 #define RME96_WCR_MASTER    (1 << 15)
 111 #define RME96_WCR_PD        (1 << 16)
 112 #define RME96_WCR_INP_0     (1 << 17)
 113 #define RME96_WCR_INP_1     (1 << 18)
 114 #define RME96_WCR_THRU_0    (1 << 19)
 115 #define RME96_WCR_THRU_1    (1 << 20)
 116 #define RME96_WCR_THRU_2    (1 << 21)
 117 #define RME96_WCR_THRU_3    (1 << 22)
 118 #define RME96_WCR_THRU_4    (1 << 23)
 119 #define RME96_WCR_THRU_5    (1 << 24)
 120 #define RME96_WCR_THRU_6    (1 << 25)
 121 #define RME96_WCR_THRU_7    (1 << 26)
 122 #define RME96_WCR_DOLBY     (1 << 27)
 123 #define RME96_WCR_MONITOR_0 (1 << 28)
 124 #define RME96_WCR_MONITOR_1 (1 << 29)
 125 #define RME96_WCR_ISEL      (1 << 30)
 126 #define RME96_WCR_IDIS      (1 << 31)
 127
 128 #define RME96_WCR_BITPOS_GAIN_0 2
 129 #define RME96_WCR_BITPOS_GAIN_1 3
 130 #define RME96_WCR_BITPOS_FREQ_0 9
 131 #define RME96_WCR_BITPOS_FREQ_1 10
 132 #define RME96_WCR_BITPOS_INP_0 17
 133 #define RME96_WCR_BITPOS_INP_1 18
 134 #define RME96_WCR_BITPOS_MONITOR_0 28
 135 #define RME96_WCR_BITPOS_MONITOR_1 29
 136
 137 /* Read control register bits */
 138 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
 139 #define RME96_RCR_IRQ_2     (1 << 16)
 140 #define RME96_RCR_T_OUT     (1 << 17)
 141 #define RME96_RCR_DEV_ID_0  (1 << 21)
 142 #define RME96_RCR_DEV_ID_1  (1 << 22)
 143 #define RME96_RCR_LOCK      (1 << 23)
 144 #define RME96_RCR_VERF      (1 << 26)
 145 #define RME96_RCR_F0        (1 << 27)
 146 #define RME96_RCR_F1        (1 << 28)
 147 #define RME96_RCR_F2        (1 << 29)
 148 #define RME96_RCR_AUTOSYNC  (1 << 30)
 149 #define RME96_RCR_IRQ       (1 << 31)
 150
 151 #define RME96_RCR_BITPOS_F0 27
 152 #define RME96_RCR_BITPOS_F1 28
 153 #define RME96_RCR_BITPOS_F2 29
 154
 155 /* Additonal register bits */
 156 #define RME96_AR_WSEL       (1 << 0)
 157 #define RME96_AR_ANALOG     (1 << 1)
 158 #define RME96_AR_FREQPAD_0  (1 << 2)
 159 #define RME96_AR_FREQPAD_1  (1 << 3)
 160 #define RME96_AR_FREQPAD_2  (1 << 4)
 161 #define RME96_AR_PD2        (1 << 5)
 162 #define RME96_AR_DAC_EN     (1 << 6)
 163 #define RME96_AR_CLATCH     (1 << 7)
 164 #define RME96_AR_CCLK       (1 << 8)
 165 #define RME96_AR_CDATA      (1 << 9)
 166
 167 #define RME96_AR_BITPOS_F0 2
 168 #define RME96_AR_BITPOS_F1 3
 169 #define RME96_AR_BITPOS_F2 4
 170
 171 /* Monitor tracks */
 172 #define RME96_MONITOR_TRACKS_1_2 0
 173 #define RME96_MONITOR_TRACKS_3_4 1
 174 #define RME96_MONITOR_TRACKS_5_6 2
 175 #define RME96_MONITOR_TRACKS_7_8 3
 176
 177 /* Attenuation */
 178 #define RME96_ATTENUATION_0 0
 179 #define RME96_ATTENUATION_6 1
 180 #define RME96_ATTENUATION_12 2
 181 #define RME96_ATTENUATION_18 3
 182
 183 /* Input types */
 184 #define RME96_INPUT_OPTICAL 0
 185 #define RME96_INPUT_COAXIAL 1
 186 #define RME96_INPUT_INTERNAL 2
 187 #define RME96_INPUT_XLR 3
 188 #define RME96_INPUT_ANALOG 4
 189
 190 /* Clock modes */
 191 #define RME96_CLOCKMODE_SLAVE 0
 192 #define RME96_CLOCKMODE_MASTER 1
 193 #define RME96_CLOCKMODE_WORDCLOCK 2
 194
 195 /* Block sizes in bytes */
 196 #define RME96_SMALL_BLOCK_SIZE 2048
 197 #define RME96_LARGE_BLOCK_SIZE 8192
 198
 199 /* Volume control */
 200 #define RME96_AD1852_VOL_BITS 14
 201 #define RME96_AD1855_VOL_BITS 10
 202
 203 /*
 204  * PCI vendor/device ids, could in the future be defined in <linux/pci.h>,
 205  * therefore #ifndef is used.
 206  */
 207 #ifndef PCI_VENDOR_ID_XILINX
 208 #define PCI_VENDOR_ID_XILINX 0x10ee
 209 #endif
 210 #ifndef PCI_DEVICE_ID_DIGI96
 211 #define PCI_DEVICE_ID_DIGI96 0x3fc0
 212 #endif
 213 #ifndef PCI_DEVICE_ID_DIGI96_8
 214 #define PCI_DEVICE_ID_DIGI96_8 0x3fc1
 215 #endif
 216 #ifndef PCI_DEVICE_ID_DIGI96_8_PRO
 217 #define PCI_DEVICE_ID_DIGI96_8_PRO 0x3fc2
 218 #endif
 219 #ifndef PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST
 220 #define PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST 0x3fc3
 221 #endif
 222
 223 typedef struct snd_rme96 {
 224         spinlock_t    lock;
 225         int irq;
 226         unsigned long port;
 227         void __iomem *iobase;
 228
 229         u32 wcreg;    /* cached write control register value */
 230         u32 wcreg_spdif;                /* S/PDIF setup */
 231         u32 wcreg_spdif_stream;         /* S/PDIF setup (temporary) */
 232         u32 rcreg;    /* cached read control register value */
 233         u32 areg;     /* cached additional register value */
 234         u16 vol[2]; /* cached volume of analog output */
 235
 236         u8 rev; /* card revision number */
 237
 238         snd_pcm_substream_t *playback_substream;
 239         snd_pcm_substream_t *capture_substream;
 240
 241         int playback_frlog; /* log2 of framesize */
 242         int capture_frlog;
 243
 244         size_t playback_periodsize; /* in bytes, zero if not used */
 245         size_t capture_periodsize; /* in bytes, zero if not used */
 246
 247         snd_card_t         *card;
 248         snd_pcm_t          *spdif_pcm;
 249         snd_pcm_t          *adat_pcm;
 250         struct pci_dev     *pci;
 251         snd_kcontrol_t     *spdif_ctl;
 252 } rme96_t;
 253
 254 static struct pci_device_id snd_rme96_ids[] = {
 255         { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96,
 256           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
 257         { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8,
 258           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
 259         { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8_PRO,
 260           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
 261         { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST,
 262           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
 263         { 0, }
 264 };
 265
 266 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
 267
 268 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
 269 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
 270 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST)
 271 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PRO || \
 272                                      (rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST)
 273 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
 274 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
 275                                   ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PRO && (rme96)->rev == 2))
 276 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
 277
 278 static int
 279 snd_rme96_playback_prepare(snd_pcm_substream_t *substream);
 280
 281 static int
 282 snd_rme96_capture_prepare(snd_pcm_substream_t *substream);
 283
 284 static int
 285 snd_rme96_playback_trigger(snd_pcm_substream_t *substream,
 286                            int cmd);
 287
 288 static int
 289 snd_rme96_capture_trigger(snd_pcm_substream_t *substream,
 290                           int cmd);
 291
 292 static snd_pcm_uframes_t
 293 snd_rme96_playback_pointer(snd_pcm_substream_t *substream);
 294
 295 static snd_pcm_uframes_t
 296 snd_rme96_capture_pointer(snd_pcm_substream_t *substream);
 297
 298 static void __devinit
 299 snd_rme96_proc_init(rme96_t *rme96);
 300
 301 static int
 302 snd_rme96_create_switches(snd_card_t *card,
 303                           rme96_t *rme96);
 304
 305 static int
 306 snd_rme96_getinputtype(rme96_t *rme96);
 307
 308 static inline unsigned int
 309 snd_rme96_playback_ptr(rme96_t *rme96)
 310 {
 311         return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
 312                 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
 313 }
 314
 315 static inline unsigned int
 316 snd_rme96_capture_ptr(rme96_t *rme96)
 317 {
 318         return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
 319                 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
 320 }
 321
 322 static int
 323 snd_rme96_ratecode(int rate)
 324 {
 325     switch (rate) {
 326     case 32000: return SNDRV_PCM_RATE_32000;
 327     case 44100: return SNDRV_PCM_RATE_44100;
 328     case 48000: return SNDRV_PCM_RATE_48000;
 329     case 64000: return SNDRV_PCM_RATE_64000;
 330     case 88200: return SNDRV_PCM_RATE_88200;
 331     case 96000: return SNDRV_PCM_RATE_96000;
 332     }
 333     return 0;
 334 }
 335
 336 static int
 337 snd_rme96_playback_silence(snd_pcm_substream_t *substream,
 338                            int channel, /* not used (interleaved data) */
 339                            snd_pcm_uframes_t pos,
 340                            snd_pcm_uframes_t count)
 341 {
 342         rme96_t *rme96 = snd_pcm_substream_chip(substream);
 343         count <<= rme96->playback_frlog;
 344         pos <<= rme96->playback_frlog;
 345         memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
 346                   0, count);
 347         return 0;
 348 }
 349
 350 static int
 351 snd_rme96_playback_copy(snd_pcm_substream_t *substream,
 352                         int channel, /* not used (interleaved data) */
 353                         snd_pcm_uframes_t pos,
 354                         void __user *src,
 355                         snd_pcm_uframes_t count)
 356 {
 357         rme96_t *rme96 = snd_pcm_substream_chip(substream);
 358         count <<= rme96->playback_frlog;
 359         pos <<= rme96->playback_frlog;
 360         copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
 361                             count);
 362         return 0;
 363 }
 364
 365 static int
 366 snd_rme96_capture_copy(snd_pcm_substream_t *substream,
 367                        int channel, /* not used (interleaved data) */
 368                        snd_pcm_uframes_t pos,
 369                        void __user *dst,
 370                        snd_pcm_uframes_t count)
 371 {
 372         rme96_t *rme96 = snd_pcm_substream_chip(substream);
 373         count <<= rme96->capture_frlog;
 374         pos <<= rme96->capture_frlog;
 375         copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
 376                             count);
 377         return 0;
 378 }
 379
 380 /*
 381  * Digital output capabilites (S/PDIF)
 382  */
 383 static snd_pcm_hardware_t snd_rme96_playback_spdif_info =
 384 {
 385         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 386                               SNDRV_PCM_INFO_MMAP_VALID |
 387                               SNDRV_PCM_INFO_INTERLEAVED |
 388                               SNDRV_PCM_INFO_PAUSE),
 389         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 390                               SNDRV_PCM_FMTBIT_S32_LE),
 391         .rates =             (SNDRV_PCM_RATE_32000 |
 392                               SNDRV_PCM_RATE_44100 |
 393                               SNDRV_PCM_RATE_48000 |
 394                               SNDRV_PCM_RATE_64000 |
 395                               SNDRV_PCM_RATE_88200 |
 396                               SNDRV_PCM_RATE_96000),
 397         .rate_min =          32000,
 398         .rate_max =          96000,
 399         .channels_min =      2,
 400         .channels_max =      2,
 401         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 402         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 403         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 404         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 405         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 406         .fifo_size =         0,
 407 };
 408
 409 /*
 410  * Digital input capabilites (S/PDIF)
 411  */
 412 static snd_pcm_hardware_t snd_rme96_capture_spdif_info =
 413 {
 414         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 415                               SNDRV_PCM_INFO_MMAP_VALID |
 416                               SNDRV_PCM_INFO_INTERLEAVED |
 417                               SNDRV_PCM_INFO_PAUSE),
 418         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 419                               SNDRV_PCM_FMTBIT_S32_LE),
 420         .rates =             (SNDRV_PCM_RATE_32000 |
 421                               SNDRV_PCM_RATE_44100 |
 422                               SNDRV_PCM_RATE_48000 |
 423                               SNDRV_PCM_RATE_64000 |
 424                               SNDRV_PCM_RATE_88200 |
 425                               SNDRV_PCM_RATE_96000),
 426         .rate_min =          32000,
 427         .rate_max =          96000,
 428         .channels_min =      2,
 429         .channels_max =      2,
 430         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 431         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 432         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 433         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 434         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 435         .fifo_size =         0,
 436 };
 437
 438 /*
 439  * Digital output capabilites (ADAT)
 440  */
 441 static snd_pcm_hardware_t snd_rme96_playback_adat_info =
 442 {
 443         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 444                               SNDRV_PCM_INFO_MMAP_VALID |
 445                               SNDRV_PCM_INFO_INTERLEAVED |
 446                               SNDRV_PCM_INFO_PAUSE),
 447         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 448                               SNDRV_PCM_FMTBIT_S32_LE),
 449         .rates =             (SNDRV_PCM_RATE_44100 |
 450                               SNDRV_PCM_RATE_48000),
 451         .rate_min =          44100,
 452         .rate_max =          48000,
 453         .channels_min =      8,
 454         .channels_max =      8,
 455         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 456         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 457         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 458         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 459         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 460         .fifo_size =         0,
 461 };
 462
 463 /*
 464  * Digital input capabilites (ADAT)
 465  */
 466 static snd_pcm_hardware_t snd_rme96_capture_adat_info =
 467 {
 468         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 469                               SNDRV_PCM_INFO_MMAP_VALID |
 470                               SNDRV_PCM_INFO_INTERLEAVED |
 471                               SNDRV_PCM_INFO_PAUSE),
 472         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 473                               SNDRV_PCM_FMTBIT_S32_LE),
 474         .rates =             (SNDRV_PCM_RATE_44100 |
 475                               SNDRV_PCM_RATE_48000),
 476         .rate_min =          44100,
 477         .rate_max =          48000,
 478         .channels_min =      8,
 479         .channels_max =      8,
 480         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 481         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 482         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 483         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 484         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 485         .fifo_size =         0,
 486 };
 487
 488 /*
 489  * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
 490  * of the AD1852 or AD1852 D/A converter on the board.  CDATA must be set up
 491  * on the falling edge of CCLK and be stable on the rising edge.  The rising
 492  * edge of CLATCH after the last data bit clocks in the whole data word.
 493  * A fast processor could probably drive the SPI interface faster than the
 494  * DAC can handle (3MHz for the 1855, unknown for the 1852).  The udelay(1)
 495  * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
 496  *
 497  * NOTE: increased delay from 1 to 10, since there where problems setting
 498  * the volume.
 499  */
 500 static void
 501 snd_rme96_write_SPI(rme96_t *rme96, u16 val)
 502 {
 503         int i;
 504
 505         for (i = 0; i < 16; i++) {
 506                 if (val & 0x8000) {
 507                         rme96->areg |= RME96_AR_CDATA;
 508                 } else {
 509                         rme96->areg &= ~RME96_AR_CDATA;
 510                 }
 511                 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
 512                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 513                 udelay(10);
 514                 rme96->areg |= RME96_AR_CCLK;
 515                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 516                 udelay(10);
 517                 val <<= 1;
 518         }
 519         rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
 520         rme96->areg |= RME96_AR_CLATCH;
 521         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 522         udelay(10);
 523         rme96->areg &= ~RME96_AR_CLATCH;
 524         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 525 }
 526
 527 static void
 528 snd_rme96_apply_dac_volume(rme96_t *rme96)
 529 {
 530         if (RME96_DAC_IS_1852(rme96)) {
 531                 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
 532                 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
 533         } else if (RME96_DAC_IS_1855(rme96)) {
 534                 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
 535                 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
 536         }
 537 }
 538
 539 static void
 540 snd_rme96_reset_dac(rme96_t *rme96)
 541 {
 542         writel(rme96->wcreg | RME96_WCR_PD,
 543                rme96->iobase + RME96_IO_CONTROL_REGISTER);
 544         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 545 }
 546
 547 static int
 548 snd_rme96_getmontracks(rme96_t *rme96)
 549 {
 550         return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
 551                 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
 552 }
 553
 554 static int
 555 snd_rme96_setmontracks(rme96_t *rme96,
 556                        int montracks)
 557 {
 558         if (montracks & 1) {
 559                 rme96->wcreg |= RME96_WCR_MONITOR_0;
 560         } else {
 561                 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
 562         }
 563         if (montracks & 2) {
 564                 rme96->wcreg |= RME96_WCR_MONITOR_1;
 565         } else {
 566                 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
 567         }
 568         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 569         return 0;
 570 }
 571
 572 static int
 573 snd_rme96_getattenuation(rme96_t *rme96)
 574 {
 575         return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
 576                 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
 577 }
 578
 579 static int
 580 snd_rme96_setattenuation(rme96_t *rme96,
 581                          int attenuation)
 582 {
 583         switch (attenuation) {
 584         case 0:
 585                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
 586                         ~RME96_WCR_GAIN_1;
 587                 break;
 588         case 1:
 589                 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
 590                         ~RME96_WCR_GAIN_1;
 591                 break;
 592         case 2:
 593                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
 594                         RME96_WCR_GAIN_1;
 595                 break;
 596         case 3:
 597                 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
 598                         RME96_WCR_GAIN_1;
 599                 break;
 600         default:
 601                 return -EINVAL;
 602         }
 603         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 604         return 0;
 605 }
 606
 607 static int
 608 snd_rme96_capture_getrate(rme96_t *rme96,
 609                           int *is_adat)
 610 {
 611         int n, rate;
 612
 613         *is_adat = 0;
 614         if (rme96->areg & RME96_AR_ANALOG) {
 615                 /* Analog input, overrides S/PDIF setting */
 616                 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
 617                         (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
 618                 switch (n) {
 619                 case 1:
 620                         rate = 32000;
 621                         break;
 622                 case 2:
 623                         rate = 44100;
 624                         break;
 625                 case 3:
 626                         rate = 48000;
 627                         break;
 628                 default:
 629                         return -1;
 630                 }
 631                 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
 632         }
 633
 634         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
 635         if (rme96->rcreg & RME96_RCR_LOCK) {
 636                 /* ADAT rate */
 637                 *is_adat = 1;
 638                 if (rme96->rcreg & RME96_RCR_T_OUT) {
 639                         return 48000;
 640                 }
 641                 return 44100;
 642         }
 643
 644         if (rme96->rcreg & RME96_RCR_VERF) {
 645                 return -1;
 646         }
 647
 648         /* S/PDIF rate */
 649         n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
 650                 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
 651                 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
 652
 653         switch (n) {
 654         case 0:
 655                 if (rme96->rcreg & RME96_RCR_T_OUT) {
 656                         return 64000;
 657                 }
 658                 return -1;
 659         case 3: return 96000;
 660         case 4: return 88200;
 661         case 5: return 48000;
 662         case 6: return 44100;
 663         case 7: return 32000;
 664         default:
 665                 break;
 666         }
 667         return -1;
 668 }
 669
 670 static int
 671 snd_rme96_playback_getrate(rme96_t *rme96)
 672 {
 673         int rate, dummy;
 674
 675         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
 676             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
 677             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
 678         {
 679                 /* slave clock */
 680                 return rate;
 681         }
 682         rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
 683                 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
 684         switch (rate) {
 685         case 1:
 686                 rate = 32000;
 687                 break;
 688         case 2:
 689                 rate = 44100;
 690                 break;
 691         case 3:
 692                 rate = 48000;
 693                 break;
 694         default:
 695                 return -1;
 696         }
 697         return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
 698 }
 699
 700 static int
 701 snd_rme96_playback_setrate(rme96_t *rme96,
 702                            int rate)
 703 {
 704         int ds;
 705
 706         ds = rme96->wcreg & RME96_WCR_DS;
 707         switch (rate) {
 708         case 32000:
 709                 rme96->wcreg &= ~RME96_WCR_DS;
 710                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
 711                         ~RME96_WCR_FREQ_1;
 712                 break;
 713         case 44100:
 714                 rme96->wcreg &= ~RME96_WCR_DS;
 715                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
 716                         ~RME96_WCR_FREQ_0;
 717                 break;
 718         case 48000:
 719                 rme96->wcreg &= ~RME96_WCR_DS;
 720                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
 721                         RME96_WCR_FREQ_1;
 722                 break;
 723         case 64000:
 724                 rme96->wcreg |= RME96_WCR_DS;
 725                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
 726                         ~RME96_WCR_FREQ_1;
 727                 break;
 728         case 88200:
 729                 rme96->wcreg |= RME96_WCR_DS;
 730                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
 731                         ~RME96_WCR_FREQ_0;
 732                 break;
 733         case 96000:
 734                 rme96->wcreg |= RME96_WCR_DS;
 735                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
 736                         RME96_WCR_FREQ_1;
 737                 break;
 738         default:
 739                 return -EINVAL;
 740         }
 741         if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
 742             (ds && !(rme96->wcreg & RME96_WCR_DS)))
 743         {
 744                 /* change to/from double-speed: reset the DAC (if available) */
 745                 snd_rme96_reset_dac(rme96);
 746         } else {
 747                 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 748         }
 749         return 0;
 750 }
 751
 752 static int
 753 snd_rme96_capture_analog_setrate(rme96_t *rme96,
 754                                  int rate)
 755 {
 756         switch (rate) {
 757         case 32000:
 758                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
 759                                ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 760                 break;
 761         case 44100:
 762                 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
 763                                RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 764                 break;
 765         case 48000:
 766                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
 767                                RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 768                 break;
 769         case 64000:
 770                 if (rme96->rev < 4) {
 771                         return -EINVAL;
 772                 }
 773                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
 774                                ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 775                 break;
 776         case 88200:
 777                 if (rme96->rev < 4) {
 778                         return -EINVAL;
 779                 }
 780                 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
 781                                RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 782                 break;
 783         case 96000:
 784                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
 785                                RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 786                 break;
 787         default:
 788                 return -EINVAL;
 789         }
 790         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 791         return 0;
 792 }
 793
 794 static int
 795 snd_rme96_setclockmode(rme96_t *rme96,
 796                        int mode)
 797 {
 798         switch (mode) {
 799         case RME96_CLOCKMODE_SLAVE:
 800                 /* AutoSync */
 801                 rme96->wcreg &= ~RME96_WCR_MASTER;
 802                 rme96->areg &= ~RME96_AR_WSEL;
 803                 break;
 804         case RME96_CLOCKMODE_MASTER:
 805                 /* Internal */
 806                 rme96->wcreg |= RME96_WCR_MASTER;
 807                 rme96->areg &= ~RME96_AR_WSEL;
 808                 break;
 809         case RME96_CLOCKMODE_WORDCLOCK:
 810                 /* Word clock is a master mode */
 811                 rme96->wcreg |= RME96_WCR_MASTER;
 812                 rme96->areg |= RME96_AR_WSEL;
 813                 break;
 814         default:
 815                 return -EINVAL;
 816         }
 817         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 818         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 819         return 0;
 820 }
 821
 822 static int
 823 snd_rme96_getclockmode(rme96_t *rme96)
 824 {
 825         if (rme96->areg & RME96_AR_WSEL) {
 826                 return RME96_CLOCKMODE_WORDCLOCK;
 827         }
 828         return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
 829                 RME96_CLOCKMODE_SLAVE;
 830 }
 831
 832 static int
 833 snd_rme96_setinputtype(rme96_t *rme96,
 834                        int type)
 835 {
 836         int n;
 837
 838         switch (type) {
 839         case RME96_INPUT_OPTICAL:
 840                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
 841                         ~RME96_WCR_INP_1;
 842                 break;
 843         case RME96_INPUT_COAXIAL:
 844                 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
 845                         ~RME96_WCR_INP_1;
 846                 break;
 847         case RME96_INPUT_INTERNAL:
 848                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
 849                         RME96_WCR_INP_1;
 850                 break;
 851         case RME96_INPUT_XLR:
 852                 if ((rme96->pci->device != PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST &&
 853                      rme96->pci->device != PCI_DEVICE_ID_DIGI96_8_PRO) ||
 854                     (rme96->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST &&
 855                      rme96->rev > 4))
 856                 {
 857                         /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
 858                         return -EINVAL;
 859                 }
 860                 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
 861                         RME96_WCR_INP_1;
 862                 break;
 863         case RME96_INPUT_ANALOG:
 864                 if (!RME96_HAS_ANALOG_IN(rme96)) {
 865                         return -EINVAL;
 866                 }
 867                 rme96->areg |= RME96_AR_ANALOG;
 868                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 869                 if (rme96->rev < 4) {
 870                         /*
 871                          * Revision less than 004 does not support 64 and
 872                          * 88.2 kHz
 873                          */
 874                         if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
 875                                 snd_rme96_capture_analog_setrate(rme96, 44100);
 876                         }
 877                         if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
 878                                 snd_rme96_capture_analog_setrate(rme96, 32000);
 879                         }
 880                 }
 881                 return 0;
 882         default:
 883                 return -EINVAL;
 884         }
 885         if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
 886                 rme96->areg &= ~RME96_AR_ANALOG;
 887                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 888         }
 889         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 890         return 0;
 891 }
 892
 893 static int
 894 snd_rme96_getinputtype(rme96_t *rme96)
 895 {
 896         if (rme96->areg & RME96_AR_ANALOG) {
 897                 return RME96_INPUT_ANALOG;
 898         }
 899         return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
 900                 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
 901 }
 902
 903 static void
 904 snd_rme96_setframelog(rme96_t *rme96,
 905                       int n_channels,
 906                       int is_playback)
 907 {
 908         int frlog;
 909
 910         if (n_channels == 2) {
 911                 frlog = 1;
 912         } else {
 913                 /* assume 8 channels */
 914                 frlog = 3;
 915         }
 916         if (is_playback) {
 917                 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
 918                 rme96->playback_frlog = frlog;
 919         } else {
 920                 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
 921                 rme96->capture_frlog = frlog;
 922         }
 923 }
 924
 925 static int
 926 snd_rme96_playback_setformat(rme96_t *rme96,
 927                              int format)
 928 {
 929         switch (format) {
 930         case SNDRV_PCM_FORMAT_S16_LE:
 931                 rme96->wcreg &= ~RME96_WCR_MODE24;
 932                 break;
 933         case SNDRV_PCM_FORMAT_S32_LE:
 934                 rme96->wcreg |= RME96_WCR_MODE24;
 935                 break;
 936         default:
 937                 return -EINVAL;
 938         }
 939         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 940         return 0;
 941 }
 942
 943 static int
 944 snd_rme96_capture_setformat(rme96_t *rme96,
 945                             int format)
 946 {
 947         switch (format) {
 948         case SNDRV_PCM_FORMAT_S16_LE:
 949                 rme96->wcreg &= ~RME96_WCR_MODE24_2;
 950                 break;
 951         case SNDRV_PCM_FORMAT_S32_LE:
 952                 rme96->wcreg |= RME96_WCR_MODE24_2;
 953                 break;
 954         default:
 955                 return -EINVAL;
 956         }
 957         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 958         return 0;
 959 }
 960
 961 static void
 962 snd_rme96_set_period_properties(rme96_t *rme96,
 963                                 size_t period_bytes)
 964 {
 965         switch (period_bytes) {
 966         case RME96_LARGE_BLOCK_SIZE:
 967                 rme96->wcreg &= ~RME96_WCR_ISEL;
 968                 break;
 969         case RME96_SMALL_BLOCK_SIZE:
 970                 rme96->wcreg |= RME96_WCR_ISEL;
 971                 break;
 972         default:
 973                 snd_BUG();
 974                 break;
 975         }
 976         rme96->wcreg &= ~RME96_WCR_IDIS;
 977         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 978 }
 979
 980 static int
 981 snd_rme96_playback_hw_params(snd_pcm_substream_t *substream,
 982                              snd_pcm_hw_params_t *params)
 983 {
 984         rme96_t *rme96 = snd_pcm_substream_chip(substream);
 985         snd_pcm_runtime_t *runtime = substream->runtime;
 986         int err, rate, dummy;
 987
 988         runtime->dma_area = (void __force *)(rme96->iobase +
 989                                              RME96_IO_PLAY_BUFFER);
 990         runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
 991         runtime->dma_bytes = RME96_BUFFER_SIZE;
 992
 993         spin_lock_irq(&rme96->lock);
 994         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
 995             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
 996             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
 997         {
 998                 /* slave clock */
 999                 if ((int)params_rate(params) != rate) {
1000                         spin_unlock_irq(&rme96->lock);
1001                         return -EIO;
1002                 }
1003         } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
1004                 spin_unlock_irq(&rme96->lock);
1005                 return err;
1006         }
1007         if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
1008                 spin_unlock_irq(&rme96->lock);
1009                 return err;
1010         }
1011         snd_rme96_setframelog(rme96, params_channels(params), 1);
1012         if (rme96->capture_periodsize != 0) {
1013                 if (params_period_size(params) << rme96->playback_frlog !=
1014                     rme96->capture_periodsize)
1015                 {
1016                         spin_unlock_irq(&rme96->lock);
1017                         return -EBUSY;
1018                 }
1019         }
1020         rme96->playback_periodsize =
1021                 params_period_size(params) << rme96->playback_frlog;
1022         snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1023         /* S/PDIF setup */
1024         if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1025                 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1026                 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1027         }
1028         spin_unlock_irq(&rme96->lock);
1029
1030         return 0;
1031 }
1032
1033 static int
1034 snd_rme96_capture_hw_params(snd_pcm_substream_t *substream,
1035                             snd_pcm_hw_params_t *params)
1036 {
1037         rme96_t *rme96 = snd_pcm_substream_chip(substream);
1038         snd_pcm_runtime_t *runtime = substream->runtime;
1039         int err, isadat, rate;
1040
1041         runtime->dma_area = (void __force *)(rme96->iobase +
1042                                              RME96_IO_REC_BUFFER);
1043         runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1044         runtime->dma_bytes = RME96_BUFFER_SIZE;
1045
1046         spin_lock_irq(&rme96->lock);
1047         if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1048                 spin_unlock_irq(&rme96->lock);
1049                 return err;
1050         }
1051         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1052                 if ((err = snd_rme96_capture_analog_setrate(rme96,
1053                                                             params_rate(params))) < 0)
1054                 {
1055                         spin_unlock_irq(&rme96->lock);
1056                         return err;
1057                 }
1058         } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1059                 if ((int)params_rate(params) != rate) {
1060                         spin_unlock_irq(&rme96->lock);
1061                         return -EIO;
1062                 }
1063                 if ((isadat && runtime->hw.channels_min == 2) ||
1064                     (!isadat && runtime->hw.channels_min == 8))
1065                 {
1066                         spin_unlock_irq(&rme96->lock);
1067                         return -EIO;
1068                 }
1069         }
1070         snd_rme96_setframelog(rme96, params_channels(params), 0);
1071         if (rme96->playback_periodsize != 0) {
1072                 if (params_period_size(params) << rme96->capture_frlog !=
1073                     rme96->playback_periodsize)
1074                 {
1075                         spin_unlock_irq(&rme96->lock);
1076                         return -EBUSY;
1077                 }
1078         }
1079         rme96->capture_periodsize =
1080                 params_period_size(params) << rme96->capture_frlog;
1081         snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1082         spin_unlock_irq(&rme96->lock);
1083
1084         return 0;
1085 }
1086
1087 static void
1088 snd_rme96_playback_start(rme96_t *rme96,
1089                          int from_pause)
1090 {
1091         if (!from_pause) {
1092                 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1093         }
1094
1095         rme96->wcreg |= RME96_WCR_START;
1096         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1097 }
1098
1099 static void
1100 snd_rme96_capture_start(rme96_t *rme96,
1101                         int from_pause)
1102 {
1103         if (!from_pause) {
1104                 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1105         }
1106
1107         rme96->wcreg |= RME96_WCR_START_2;
1108         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1109 }
1110
1111 static void
1112 snd_rme96_playback_stop(rme96_t *rme96)
1113 {
1114         /*
1115          * Check if there is an unconfirmed IRQ, if so confirm it, or else
1116          * the hardware will not stop generating interrupts
1117          */
1118         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1119         if (rme96->rcreg & RME96_RCR_IRQ) {
1120                 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1121         }
1122         rme96->wcreg &= ~RME96_WCR_START;
1123         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1124 }
1125
1126 static void
1127 snd_rme96_capture_stop(rme96_t *rme96)
1128 {
1129         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1130         if (rme96->rcreg & RME96_RCR_IRQ_2) {
1131                 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1132         }
1133         rme96->wcreg &= ~RME96_WCR_START_2;
1134         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1135 }
1136
1137 static irqreturn_t
1138 snd_rme96_interrupt(int irq,
1139                     void *dev_id,
1140                     struct pt_regs *regs)
1141 {
1142         rme96_t *rme96 = (rme96_t *)dev_id;
1143
1144         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1145         /* fastpath out, to ease interrupt sharing */
1146         if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1147               (rme96->rcreg & RME96_RCR_IRQ_2)))
1148         {
1149                 return IRQ_NONE;
1150         }
1151
1152         if (rme96->rcreg & RME96_RCR_IRQ) {
1153                 /* playback */
1154                 snd_pcm_period_elapsed(rme96->playback_substream);
1155                 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1156         }
1157         if (rme96->rcreg & RME96_RCR_IRQ_2) {
1158                 /* capture */
1159                 snd_pcm_period_elapsed(rme96->capture_substream);
1160                 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1161         }
1162         return IRQ_HANDLED;
1163 }
1164
1165 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1166
1167 static snd_pcm_hw_constraint_list_t hw_constraints_period_bytes = {
1168         .count = ARRAY_SIZE(period_bytes),
1169         .list = period_bytes,
1170         .mask = 0
1171 };
1172
1173 static int
1174 snd_rme96_playback_spdif_open(snd_pcm_substream_t *substream)
1175 {
1176         int rate, dummy;
1177         rme96_t *rme96 = snd_pcm_substream_chip(substream);
1178         snd_pcm_runtime_t *runtime = substream->runtime;
1179
1180         snd_pcm_set_sync(substream);
1181
1182         spin_lock_irq(&rme96->lock);
1183         if (rme96->playback_substream != NULL) {
1184                 spin_unlock_irq(&rme96->lock);
1185                 return -EBUSY;
1186         }
1187         rme96->wcreg &= ~RME96_WCR_ADAT;
1188         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1189         rme96->playback_substream = substream;
1190         spin_unlock_irq(&rme96->lock);
1191
1192         runtime->hw = snd_rme96_playback_spdif_info;
1193         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1194             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1195             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1196         {
1197                 /* slave clock */
1198                 runtime->hw.rates = snd_rme96_ratecode(rate);
1199                 runtime->hw.rate_min = rate;
1200                 runtime->hw.rate_max = rate;
1201         }
1202         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1203         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1204
1205         rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1206         rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1207         snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1208                        SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1209         return 0;
1210 }
1211
1212 static int
1213 snd_rme96_capture_spdif_open(snd_pcm_substream_t *substream)
1214 {
1215         int isadat, rate;
1216         rme96_t *rme96 = snd_pcm_substream_chip(substream);
1217         snd_pcm_runtime_t *runtime = substream->runtime;
1218
1219         snd_pcm_set_sync(substream);
1220
1221         runtime->hw = snd_rme96_capture_spdif_info;
1222         if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1223             (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1224         {
1225                 if (isadat) {
1226                         return -EIO;
1227                 }
1228                 runtime->hw.rates = snd_rme96_ratecode(rate);
1229                 runtime->hw.rate_min = rate;
1230                 runtime->hw.rate_max = rate;
1231         }
1232
1233         spin_lock_irq(&rme96->lock);
1234         if (rme96->capture_substream != NULL) {
1235                 spin_unlock_irq(&rme96->lock);
1236                 return -EBUSY;
1237         }
1238         rme96->capture_substream = substream;
1239         spin_unlock_irq(&rme96->lock);
1240
1241         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1242         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1243
1244         return 0;
1245 }
1246
1247 static int
1248 snd_rme96_playback_adat_open(snd_pcm_substream_t *substream)
1249 {
1250         int rate, dummy;
1251         rme96_t *rme96 = snd_pcm_substream_chip(substream);
1252         snd_pcm_runtime_t *runtime = substream->runtime;
1253
1254         snd_pcm_set_sync(substream);
1255
1256         spin_lock_irq(&rme96->lock);
1257         if (rme96->playback_substream != NULL) {
1258                 spin_unlock_irq(&rme96->lock);
1259                 return -EBUSY;
1260         }
1261         rme96->wcreg |= RME96_WCR_ADAT;
1262         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1263         rme96->playback_substream = substream;
1264         spin_unlock_irq(&rme96->lock);
1265
1266         runtime->hw = snd_rme96_playback_adat_info;
1267         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1268             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1269             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1270         {
1271                 /* slave clock */
1272                 runtime->hw.rates = snd_rme96_ratecode(rate);
1273                 runtime->hw.rate_min = rate;
1274                 runtime->hw.rate_max = rate;
1275         }
1276         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1277         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1278         return 0;
1279 }
1280
1281 static int
1282 snd_rme96_capture_adat_open(snd_pcm_substream_t *substream)
1283 {
1284         int isadat, rate;
1285         rme96_t *rme96 = snd_pcm_substream_chip(substream);
1286         snd_pcm_runtime_t *runtime = substream->runtime;
1287
1288         snd_pcm_set_sync(substream);
1289
1290         runtime->hw = snd_rme96_capture_adat_info;
1291         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1292                 /* makes no sense to use analog input. Note that analog
1293                    expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1294                 return -EIO;
1295         }
1296         if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1297                 if (!isadat) {
1298                         return -EIO;
1299                 }
1300                 runtime->hw.rates = snd_rme96_ratecode(rate);
1301                 runtime->hw.rate_min = rate;
1302                 runtime->hw.rate_max = rate;
1303         }
1304
1305         spin_lock_irq(&rme96->lock);
1306         if (rme96->capture_substream != NULL) {
1307                 spin_unlock_irq(&rme96->lock);
1308                 return -EBUSY;
1309         }
1310         rme96->capture_substream = substream;
1311         spin_unlock_irq(&rme96->lock);
1312
1313         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1314         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1315         return 0;
1316 }
1317
1318 static int
1319 snd_rme96_playback_close(snd_pcm_substream_t *substream)
1320 {
1321         rme96_t *rme96 = snd_pcm_substream_chip(substream);
1322         int spdif = 0;
1323
1324         spin_lock_irq(&rme96->lock);
1325         if (RME96_ISPLAYING(rme96)) {
1326                 snd_rme96_playback_stop(rme96);
1327         }
1328         rme96->playback_substream = NULL;
1329         rme96->playback_periodsize = 0;
1330         spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1331         spin_unlock_irq(&rme96->lock);
1332         if (spdif) {
1333                 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1334                 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1335                                SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1336         }
1337         return 0;
1338 }
1339
1340 static int
1341 snd_rme96_capture_close(snd_pcm_substream_t *substream)
1342 {
1343         rme96_t *rme96 = snd_pcm_substream_chip(substream);
1344
1345         spin_lock_irq(&rme96->lock);
1346         if (RME96_ISRECORDING(rme96)) {
1347                 snd_rme96_capture_stop(rme96);
1348         }
1349         rme96->capture_substream = NULL;
1350         rme96->capture_periodsize = 0;
1351         spin_unlock_irq(&rme96->lock);
1352         return 0;
1353 }
1354
1355 static int
1356 snd_rme96_playback_prepare(snd_pcm_substream_t *substream)
1357 {
1358         rme96_t *rme96 = snd_pcm_substream_chip(substream);
1359
1360         spin_lock_irq(&rme96->lock);
1361         if (RME96_ISPLAYING(rme96)) {
1362                 snd_rme96_playback_stop(rme96);
1363         }
1364         writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1365         spin_unlock_irq(&rme96->lock);
1366         return 0;
1367 }
1368
1369 static int
1370 snd_rme96_capture_prepare(snd_pcm_substream_t *substream)
1371 {
1372         rme96_t *rme96 = snd_pcm_substream_chip(substream);
1373
1374         spin_lock_irq(&rme96->lock);
1375         if (RME96_ISRECORDING(rme96)) {
1376                 snd_rme96_capture_stop(rme96);
1377         }
1378         writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1379         spin_unlock_irq(&rme96->lock);
1380         return 0;
1381 }
1382
1383 static int
1384 snd_rme96_playback_trigger(snd_pcm_substream_t *substream,
1385                            int cmd)
1386 {
1387         rme96_t *rme96 = snd_pcm_substream_chip(substream);
1388
1389         switch (cmd) {
1390         case SNDRV_PCM_TRIGGER_START:
1391                 if (!RME96_ISPLAYING(rme96)) {
1392                         if (substream != rme96->playback_substream) {
1393                                 return -EBUSY;
1394                         }
1395                         snd_rme96_playback_start(rme96, 0);
1396                 }
1397                 break;
1398
1399         case SNDRV_PCM_TRIGGER_STOP:
1400                 if (RME96_ISPLAYING(rme96)) {
1401                         if (substream != rme96->playback_substream) {
1402                                 return -EBUSY;
1403                         }
1404                         snd_rme96_playback_stop(rme96);
1405                 }
1406                 break;
1407
1408         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1409                 if (RME96_ISPLAYING(rme96)) {
1410                         snd_rme96_playback_stop(rme96);
1411                 }
1412                 break;
1413
1414         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1415                 if (!RME96_ISPLAYING(rme96)) {
1416                         snd_rme96_playback_start(rme96, 1);
1417                 }
1418                 break;
1419
1420         default:
1421                 return -EINVAL;
1422         }
1423         return 0;
1424 }
1425
1426 static int
1427 snd_rme96_capture_trigger(snd_pcm_substream_t *substream,
1428                           int cmd)
1429 {
1430         rme96_t *rme96 = snd_pcm_substream_chip(substream);
1431
1432         switch (cmd) {
1433         case SNDRV_PCM_TRIGGER_START:
1434                 if (!RME96_ISRECORDING(rme96)) {
1435                         if (substream != rme96->capture_substream) {
1436                                 return -EBUSY;
1437                         }
1438                         snd_rme96_capture_start(rme96, 0);
1439                 }
1440                 break;
1441
1442         case SNDRV_PCM_TRIGGER_STOP:
1443                 if (RME96_ISRECORDING(rme96)) {
1444                         if (substream != rme96->capture_substream) {
1445                                 return -EBUSY;
1446                         }
1447                         snd_rme96_capture_stop(rme96);
1448                 }
1449                 break;
1450
1451         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1452                 if (RME96_ISRECORDING(rme96)) {
1453                         snd_rme96_capture_stop(rme96);
1454                 }
1455                 break;
1456
1457         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1458                 if (!RME96_ISRECORDING(rme96)) {
1459                         snd_rme96_capture_start(rme96, 1);
1460                 }
1461                 break;
1462
1463         default:
1464                 return -EINVAL;
1465         }
1466
1467         return 0;
1468 }
1469
1470 static snd_pcm_uframes_t
1471 snd_rme96_playback_pointer(snd_pcm_substream_t *substream)
1472 {
1473         rme96_t *rme96 = snd_pcm_substream_chip(substream);
1474         return snd_rme96_playback_ptr(rme96);
1475 }
1476
1477 static snd_pcm_uframes_t
1478 snd_rme96_capture_pointer(snd_pcm_substream_t *substream)
1479 {
1480         rme96_t *rme96 = snd_pcm_substream_chip(substream);
1481         return snd_rme96_capture_ptr(rme96);
1482 }
1483
1484 static snd_pcm_ops_t snd_rme96_playback_spdif_ops = {
1485         .open =         snd_rme96_playback_spdif_open,
1486         .close =        snd_rme96_playback_close,
1487         .ioctl =        snd_pcm_lib_ioctl,
1488         .hw_params =    snd_rme96_playback_hw_params,
1489         .prepare =      snd_rme96_playback_prepare,
1490         .trigger =      snd_rme96_playback_trigger,
1491         .pointer =      snd_rme96_playback_pointer,
1492         .copy =         snd_rme96_playback_copy,
1493         .silence =      snd_rme96_playback_silence,
1494         .mmap =         snd_pcm_lib_mmap_iomem,
1495 };
1496
1497 static snd_pcm_ops_t snd_rme96_capture_spdif_ops = {
1498         .open =         snd_rme96_capture_spdif_open,
1499         .close =        snd_rme96_capture_close,
1500         .ioctl =        snd_pcm_lib_ioctl,
1501         .hw_params =    snd_rme96_capture_hw_params,
1502         .prepare =      snd_rme96_capture_prepare,
1503         .trigger =      snd_rme96_capture_trigger,
1504         .pointer =      snd_rme96_capture_pointer,
1505         .copy =         snd_rme96_capture_copy,
1506         .mmap =         snd_pcm_lib_mmap_iomem,
1507 };
1508
1509 static snd_pcm_ops_t snd_rme96_playback_adat_ops = {
1510         .open =         snd_rme96_playback_adat_open,
1511         .close =        snd_rme96_playback_close,
1512         .ioctl =        snd_pcm_lib_ioctl,
1513         .hw_params =    snd_rme96_playback_hw_params,
1514         .prepare =      snd_rme96_playback_prepare,
1515         .trigger =      snd_rme96_playback_trigger,
1516         .pointer =      snd_rme96_playback_pointer,
1517         .copy =         snd_rme96_playback_copy,
1518         .silence =      snd_rme96_playback_silence,
1519         .mmap =         snd_pcm_lib_mmap_iomem,
1520 };
1521
1522 static snd_pcm_ops_t snd_rme96_capture_adat_ops = {
1523         .open =         snd_rme96_capture_adat_open,
1524         .close =        snd_rme96_capture_close,
1525         .ioctl =        snd_pcm_lib_ioctl,
1526         .hw_params =    snd_rme96_capture_hw_params,
1527         .prepare =      snd_rme96_capture_prepare,
1528         .trigger =      snd_rme96_capture_trigger,
1529         .pointer =      snd_rme96_capture_pointer,
1530         .copy =         snd_rme96_capture_copy,
1531         .mmap =         snd_pcm_lib_mmap_iomem,
1532 };
1533
1534 static void
1535 snd_rme96_free(void *private_data)
1536 {
1537         rme96_t *rme96 = (rme96_t *)private_data;
1538
1539         if (rme96 == NULL) {
1540                 return;
1541         }
1542         if (rme96->irq >= 0) {
1543                 snd_rme96_playback_stop(rme96);
1544                 snd_rme96_capture_stop(rme96);
1545                 rme96->areg &= ~RME96_AR_DAC_EN;
1546                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1547                 free_irq(rme96->irq, (void *)rme96);
1548                 rme96->irq = -1;
1549         }
1550         if (rme96->iobase) {
1551                 iounmap(rme96->iobase);
1552                 rme96->iobase = NULL;
1553         }
1554         if (rme96->port) {
1555                 pci_release_regions(rme96->pci);
1556                 rme96->port = 0;
1557         }
1558         pci_disable_device(rme96->pci);
1559 }
1560
1561 static void
1562 snd_rme96_free_spdif_pcm(snd_pcm_t *pcm)
1563 {
1564         rme96_t *rme96 = (rme96_t *) pcm->private_data;
1565         rme96->spdif_pcm = NULL;
1566 }
1567
1568 static void
1569 snd_rme96_free_adat_pcm(snd_pcm_t *pcm)
1570 {
1571         rme96_t *rme96 = (rme96_t *) pcm->private_data;
1572         rme96->adat_pcm = NULL;
1573 }
1574
1575 static int __devinit
1576 snd_rme96_create(rme96_t *rme96)
1577 {
1578         struct pci_dev *pci = rme96->pci;
1579         int err;
1580
1581         rme96->irq = -1;
1582         spin_lock_init(&rme96->lock);
1583
1584         if ((err = pci_enable_device(pci)) < 0)
1585                 return err;
1586
1587         if ((err = pci_request_regions(pci, "RME96")) < 0)
1588                 return err;
1589         rme96->port = pci_resource_start(rme96->pci, 0);
1590
1591         if (request_irq(pci->irq, snd_rme96_interrupt, SA_INTERRUPT|SA_SHIRQ, "RME96", (void *)rme96)) {
1592                 snd_printk("unable to grab IRQ %d\n", pci->irq);
1593                 return -EBUSY;
1594         }
1595         rme96->irq = pci->irq;
1596
1597         if ((rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE)) == 0) {
1598                 snd_printk("unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1599                 return -ENOMEM;
1600         }
1601
1602         /* read the card's revision number */
1603         pci_read_config_byte(pci, 8, &rme96->rev);
1604
1605         /* set up ALSA pcm device for S/PDIF */
1606         if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1607                                1, 1, &rme96->spdif_pcm)) < 0)
1608         {
1609                 return err;
1610         }
1611         rme96->spdif_pcm->private_data = rme96;
1612         rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1613         strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1614         snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1615         snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1616
1617         rme96->spdif_pcm->info_flags = 0;
1618
1619         /* set up ALSA pcm device for ADAT */
1620         if (pci->device == PCI_DEVICE_ID_DIGI96) {
1621                 /* ADAT is not available on the base model */
1622                 rme96->adat_pcm = NULL;
1623         } else {
1624                 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1625                                        1, 1, &rme96->adat_pcm)) < 0)
1626                 {
1627                         return err;
1628                 }
1629                 rme96->adat_pcm->private_data = rme96;
1630                 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1631                 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1632                 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1633                 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1634
1635                 rme96->adat_pcm->info_flags = 0;
1636         }
1637
1638         rme96->playback_periodsize = 0;
1639         rme96->capture_periodsize = 0;
1640
1641         /* make sure playback/capture is stopped, if by some reason active */
1642         snd_rme96_playback_stop(rme96);
1643         snd_rme96_capture_stop(rme96);
1644
1645         /* set default values in registers */
1646         rme96->wcreg =
1647                 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1648                 RME96_WCR_SEL |    /* normal playback */
1649                 RME96_WCR_MASTER | /* set to master clock mode */
1650                 RME96_WCR_INP_0;   /* set coaxial input */
1651
1652         rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1653
1654         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1655         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1656
1657         /* reset the ADC */
1658         writel(rme96->areg | RME96_AR_PD2,
1659                rme96->iobase + RME96_IO_ADDITIONAL_REG);
1660         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1661
1662         /* reset and enable the DAC (order is important). */
1663         snd_rme96_reset_dac(rme96);
1664         rme96->areg |= RME96_AR_DAC_EN;
1665         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1666
1667         /* reset playback and record buffer pointers */
1668         writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1669         writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1670
1671         /* reset volume */
1672         rme96->vol[0] = rme96->vol[1] = 0;
1673         if (RME96_HAS_ANALOG_OUT(rme96)) {
1674                 snd_rme96_apply_dac_volume(rme96);
1675         }
1676
1677         /* init switch interface */
1678         if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1679                 return err;
1680         }
1681
1682         /* init proc interface */
1683         snd_rme96_proc_init(rme96);
1684
1685         return 0;
1686 }
1687
1688 /*
1689  * proc interface
1690  */
1691
1692 static void
1693 snd_rme96_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
1694 {
1695         int n;
1696         rme96_t *rme96 = (rme96_t *)entry->private_data;
1697
1698         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1699
1700         snd_iprintf(buffer, rme96->card->longname);
1701         snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1702
1703         snd_iprintf(buffer, "\nGeneral settings\n");
1704         if (rme96->wcreg & RME96_WCR_IDIS) {
1705                 snd_iprintf(buffer, "  period size: N/A (interrupts "
1706                             "disabled)\n");
1707         } else if (rme96->wcreg & RME96_WCR_ISEL) {
1708                 snd_iprintf(buffer, "  period size: 2048 bytes\n");
1709         } else {
1710                 snd_iprintf(buffer, "  period size: 8192 bytes\n");
1711         }
1712         snd_iprintf(buffer, "\nInput settings\n");
1713         switch (snd_rme96_getinputtype(rme96)) {
1714         case RME96_INPUT_OPTICAL:
1715                 snd_iprintf(buffer, "  input: optical");
1716                 break;
1717         case RME96_INPUT_COAXIAL:
1718                 snd_iprintf(buffer, "  input: coaxial");
1719                 break;
1720         case RME96_INPUT_INTERNAL:
1721                 snd_iprintf(buffer, "  input: internal");
1722                 break;
1723         case RME96_INPUT_XLR:
1724                 snd_iprintf(buffer, "  input: XLR");
1725                 break;
1726         case RME96_INPUT_ANALOG:
1727                 snd_iprintf(buffer, "  input: analog");
1728                 break;
1729         }
1730         if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1731                 snd_iprintf(buffer, "\n  sample rate: no valid signal\n");
1732         } else {
1733                 if (n) {
1734                         snd_iprintf(buffer, " (8 channels)\n");
1735                 } else {
1736                         snd_iprintf(buffer, " (2 channels)\n");
1737                 }
1738                 snd_iprintf(buffer, "  sample rate: %d Hz\n",
1739                             snd_rme96_capture_getrate(rme96, &n));
1740         }
1741         if (rme96->wcreg & RME96_WCR_MODE24_2) {
1742                 snd_iprintf(buffer, "  sample format: 24 bit\n");
1743         } else {
1744                 snd_iprintf(buffer, "  sample format: 16 bit\n");
1745         }
1746
1747         snd_iprintf(buffer, "\nOutput settings\n");
1748         if (rme96->wcreg & RME96_WCR_SEL) {
1749                 snd_iprintf(buffer, "  output signal: normal playback\n");
1750         } else {
1751                 snd_iprintf(buffer, "  output signal: same as input\n");
1752         }
1753         snd_iprintf(buffer, "  sample rate: %d Hz\n",
1754                     snd_rme96_playback_getrate(rme96));
1755         if (rme96->wcreg & RME96_WCR_MODE24) {
1756                 snd_iprintf(buffer, "  sample format: 24 bit\n");
1757         } else {
1758                 snd_iprintf(buffer, "  sample format: 16 bit\n");
1759         }
1760         if (rme96->areg & RME96_AR_WSEL) {
1761                 snd_iprintf(buffer, "  sample clock source: word clock\n");
1762         } else if (rme96->wcreg & RME96_WCR_MASTER) {
1763                 snd_iprintf(buffer, "  sample clock source: internal\n");
1764         } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1765                 snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to analog input setting)\n");
1766         } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1767                 snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to no valid signal)\n");
1768         } else {
1769                 snd_iprintf(buffer, "  sample clock source: autosync\n");
1770         }
1771         if (rme96->wcreg & RME96_WCR_PRO) {
1772                 snd_iprintf(buffer, "  format: AES/EBU (professional)\n");
1773         } else {
1774                 snd_iprintf(buffer, "  format: IEC958 (consumer)\n");
1775         }
1776         if (rme96->wcreg & RME96_WCR_EMP) {
1777                 snd_iprintf(buffer, "  emphasis: on\n");
1778         } else {
1779                 snd_iprintf(buffer, "  emphasis: off\n");
1780         }
1781         if (rme96->wcreg & RME96_WCR_DOLBY) {
1782                 snd_iprintf(buffer, "  non-audio (dolby): on\n");
1783         } else {
1784                 snd_iprintf(buffer, "  non-audio (dolby): off\n");
1785         }
1786         if (RME96_HAS_ANALOG_IN(rme96)) {
1787                 snd_iprintf(buffer, "\nAnalog output settings\n");
1788                 switch (snd_rme96_getmontracks(rme96)) {
1789                 case RME96_MONITOR_TRACKS_1_2:
1790                         snd_iprintf(buffer, "  monitored ADAT tracks: 1+2\n");
1791                         break;
1792                 case RME96_MONITOR_TRACKS_3_4:
1793                         snd_iprintf(buffer, "  monitored ADAT tracks: 3+4\n");
1794                         break;
1795                 case RME96_MONITOR_TRACKS_5_6:
1796                         snd_iprintf(buffer, "  monitored ADAT tracks: 5+6\n");
1797                         break;
1798                 case RME96_MONITOR_TRACKS_7_8:
1799                         snd_iprintf(buffer, "  monitored ADAT tracks: 7+8\n");
1800                         break;
1801                 }
1802                 switch (snd_rme96_getattenuation(rme96)) {
1803                 case RME96_ATTENUATION_0:
1804                         snd_iprintf(buffer, "  attenuation: 0 dB\n");
1805                         break;
1806                 case RME96_ATTENUATION_6:
1807                         snd_iprintf(buffer, "  attenuation: -6 dB\n");
1808                         break;
1809                 case RME96_ATTENUATION_12:
1810                         snd_iprintf(buffer, "  attenuation: -12 dB\n");
1811                         break;
1812                 case RME96_ATTENUATION_18:
1813                         snd_iprintf(buffer, "  attenuation: -18 dB\n");
1814                         break;
1815                 }
1816                 snd_iprintf(buffer, "  volume left: %u\n", rme96->vol[0]);
1817                 snd_iprintf(buffer, "  volume right: %u\n", rme96->vol[1]);
1818         }
1819 }
1820
1821 static void __devinit
1822 snd_rme96_proc_init(rme96_t *rme96)
1823 {
1824         snd_info_entry_t *entry;
1825
1826         if (! snd_card_proc_new(rme96->card, "rme96", &entry))
1827                 snd_info_set_text_ops(entry, rme96, 1024, snd_rme96_proc_read);
1828 }
1829
1830 /*
1831  * control interface
1832  */
1833
1834 static int
1835 snd_rme96_info_loopback_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1836 {
1837         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1838         uinfo->count = 1;
1839         uinfo->value.integer.min = 0;
1840         uinfo->value.integer.max = 1;
1841         return 0;
1842 }
1843 static int
1844 snd_rme96_get_loopback_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1845 {
1846         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
1847
1848         spin_lock_irq(&rme96->lock);
1849         ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1850         spin_unlock_irq(&rme96->lock);
1851         return 0;
1852 }
1853 static int
1854 snd_rme96_put_loopback_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1855 {
1856         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
1857         unsigned int val;
1858         int change;
1859
1860         val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1861         spin_lock_irq(&rme96->lock);
1862         val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1863         change = val != rme96->wcreg;
1864         rme96->wcreg = val;
1865         writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1866         spin_unlock_irq(&rme96->lock);
1867         return change;
1868 }
1869
1870 static int
1871 snd_rme96_info_inputtype_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1872 {
1873         static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
1874         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
1875         char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1876
1877         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1878         uinfo->count = 1;
1879         switch (rme96->pci->device) {
1880         case PCI_DEVICE_ID_DIGI96:
1881         case PCI_DEVICE_ID_DIGI96_8:
1882                 uinfo->value.enumerated.items = 3;
1883                 break;
1884         case PCI_DEVICE_ID_DIGI96_8_PRO:
1885                 uinfo->value.enumerated.items = 4;
1886                 break;
1887         case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
1888                 if (rme96->rev > 4) {
1889                         /* PST */
1890                         uinfo->value.enumerated.items = 4;
1891                         texts[3] = _texts[4]; /* Analog instead of XLR */
1892                 } else {
1893                         /* PAD */
1894                         uinfo->value.enumerated.items = 5;
1895                 }
1896                 break;
1897         default:
1898                 snd_BUG();
1899                 break;
1900         }
1901         if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
1902                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1903         }
1904         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1905         return 0;
1906 }
1907 static int
1908 snd_rme96_get_inputtype_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1909 {
1910         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
1911         unsigned int items = 3;
1912
1913         spin_lock_irq(&rme96->lock);
1914         ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1915
1916         switch (rme96->pci->device) {
1917         case PCI_DEVICE_ID_DIGI96:
1918         case PCI_DEVICE_ID_DIGI96_8:
1919                 items = 3;
1920                 break;
1921         case PCI_DEVICE_ID_DIGI96_8_PRO:
1922                 items = 4;
1923                 break;
1924         case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
1925                 if (rme96->rev > 4) {
1926                         /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1927                         if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1928                                 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1929                         }
1930                         items = 4;
1931                 } else {
1932                         items = 5;
1933                 }
1934                 break;
1935         default:
1936                 snd_BUG();
1937                 break;
1938         }
1939         if (ucontrol->value.enumerated.item[0] >= items) {
1940                 ucontrol->value.enumerated.item[0] = items - 1;
1941         }
1942
1943         spin_unlock_irq(&rme96->lock);
1944         return 0;
1945 }
1946 static int
1947 snd_rme96_put_inputtype_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1948 {
1949         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
1950         unsigned int val;
1951         int change, items = 3;
1952
1953         switch (rme96->pci->device) {
1954         case PCI_DEVICE_ID_DIGI96:
1955         case PCI_DEVICE_ID_DIGI96_8:
1956                 items = 3;
1957                 break;
1958         case PCI_DEVICE_ID_DIGI96_8_PRO:
1959                 items = 4;
1960                 break;
1961         case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
1962                 if (rme96->rev > 4) {
1963                         items = 4;
1964                 } else {
1965                         items = 5;
1966                 }
1967                 break;
1968         default:
1969                 snd_BUG();
1970                 break;
1971         }
1972         val = ucontrol->value.enumerated.item[0] % items;
1973
1974         /* special case for PST */
1975         if (rme96->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1976                 if (val == RME96_INPUT_XLR) {
1977                         val = RME96_INPUT_ANALOG;
1978                 }
1979         }
1980
1981         spin_lock_irq(&rme96->lock);
1982         change = (int)val != snd_rme96_getinputtype(rme96);
1983         snd_rme96_setinputtype(rme96, val);
1984         spin_unlock_irq(&rme96->lock);
1985         return change;
1986 }
1987
1988 static int
1989 snd_rme96_info_clockmode_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1990 {
1991         static char *texts[3] = { "AutoSync", "Internal", "Word" };
1992
1993         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1994         uinfo->count = 1;
1995         uinfo->value.enumerated.items = 3;
1996         if (uinfo->value.enumerated.item > 2) {
1997                 uinfo->value.enumerated.item = 2;
1998         }
1999         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2000         return 0;
2001 }
2002 static int
2003 snd_rme96_get_clockmode_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2004 {
2005         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2006
2007         spin_lock_irq(&rme96->lock);
2008         ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
2009         spin_unlock_irq(&rme96->lock);
2010         return 0;
2011 }
2012 static int
2013 snd_rme96_put_clockmode_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2014 {
2015         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2016         unsigned int val;
2017         int change;
2018
2019         val = ucontrol->value.enumerated.item[0] % 3;
2020         spin_lock_irq(&rme96->lock);
2021         change = (int)val != snd_rme96_getclockmode(rme96);
2022         snd_rme96_setclockmode(rme96, val);
2023         spin_unlock_irq(&rme96->lock);
2024         return change;
2025 }
2026
2027 static int
2028 snd_rme96_info_attenuation_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2029 {
2030         static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
2031
2032         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2033         uinfo->count = 1;
2034         uinfo->value.enumerated.items = 4;
2035         if (uinfo->value.enumerated.item > 3) {
2036                 uinfo->value.enumerated.item = 3;
2037         }
2038         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2039         return 0;
2040 }
2041 static int
2042 snd_rme96_get_attenuation_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2043 {
2044         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2045
2046         spin_lock_irq(&rme96->lock);
2047         ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2048         spin_unlock_irq(&rme96->lock);
2049         return 0;
2050 }
2051 static int
2052 snd_rme96_put_attenuation_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2053 {
2054         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2055         unsigned int val;
2056         int change;
2057
2058         val = ucontrol->value.enumerated.item[0] % 4;
2059         spin_lock_irq(&rme96->lock);
2060
2061         change = (int)val != snd_rme96_getattenuation(rme96);
2062         snd_rme96_setattenuation(rme96, val);
2063         spin_unlock_irq(&rme96->lock);
2064         return change;
2065 }
2066
2067 static int
2068 snd_rme96_info_montracks_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2069 {
2070         static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2071
2072         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2073         uinfo->count = 1;
2074         uinfo->value.enumerated.items = 4;
2075         if (uinfo->value.enumerated.item > 3) {
2076                 uinfo->value.enumerated.item = 3;
2077         }
2078         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2079         return 0;
2080 }
2081 static int
2082 snd_rme96_get_montracks_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2083 {
2084         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2085
2086         spin_lock_irq(&rme96->lock);
2087         ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2088         spin_unlock_irq(&rme96->lock);
2089         return 0;
2090 }
2091 static int
2092 snd_rme96_put_montracks_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2093 {
2094         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2095         unsigned int val;
2096         int change;
2097
2098         val = ucontrol->value.enumerated.item[0] % 4;
2099         spin_lock_irq(&rme96->lock);
2100         change = (int)val != snd_rme96_getmontracks(rme96);
2101         snd_rme96_setmontracks(rme96, val);
2102         spin_unlock_irq(&rme96->lock);
2103         return change;
2104 }
2105
2106 static u32 snd_rme96_convert_from_aes(snd_aes_iec958_t *aes)
2107 {
2108         u32 val = 0;
2109         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2110         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2111         if (val & RME96_WCR_PRO)
2112                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2113         else
2114                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2115         return val;
2116 }
2117
2118 static void snd_rme96_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
2119 {
2120         aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2121                          ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2122         if (val & RME96_WCR_PRO)
2123                 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2124         else
2125                 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2126 }
2127
2128 static int snd_rme96_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2129 {
2130         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2131         uinfo->count = 1;
2132         return 0;
2133 }
2134
2135 static int snd_rme96_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2136 {
2137         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2138
2139         snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2140         return 0;
2141 }
2142
2143 static int snd_rme96_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2144 {
2145         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2146         int change;
2147         u32 val;
2148
2149         val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2150         spin_lock_irq(&rme96->lock);
2151         change = val != rme96->wcreg_spdif;
2152         rme96->wcreg_spdif = val;
2153         spin_unlock_irq(&rme96->lock);
2154         return change;
2155 }
2156
2157 static int snd_rme96_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2158 {
2159         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2160         uinfo->count = 1;
2161         return 0;
2162 }
2163
2164 static int snd_rme96_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2165 {
2166         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2167
2168         snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2169         return 0;
2170 }
2171
2172 static int snd_rme96_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2173 {
2174         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2175         int change;
2176         u32 val;
2177
2178         val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2179         spin_lock_irq(&rme96->lock);
2180         change = val != rme96->wcreg_spdif_stream;
2181         rme96->wcreg_spdif_stream = val;
2182         rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2183         rme96->wcreg |= val;
2184         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2185         spin_unlock_irq(&rme96->lock);
2186         return change;
2187 }
2188
2189 static int snd_rme96_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2190 {
2191         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2192         uinfo->count = 1;
2193         return 0;
2194 }
2195
2196 static int snd_rme96_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2197 {
2198         ucontrol->value.iec958.status[0] = kcontrol->private_value;
2199         return 0;
2200 }
2201
2202 static int
2203 snd_rme96_dac_volume_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2204 {
2205         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2206
2207         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2208         uinfo->count = 2;
2209         uinfo->value.integer.min = 0;
2210         uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2211         return 0;
2212 }
2213
2214 static int
2215 snd_rme96_dac_volume_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *u)
2216 {
2217         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2218
2219         spin_lock_irq(&rme96->lock);
2220         u->value.integer.value[0] = rme96->vol[0];
2221         u->value.integer.value[1] = rme96->vol[1];
2222         spin_unlock_irq(&rme96->lock);
2223
2224         return 0;
2225 }
2226
2227 static int
2228 snd_rme96_dac_volume_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *u)
2229 {
2230         rme96_t *rme96 = snd_kcontrol_chip(kcontrol);
2231         int change = 0;
2232
2233         if (!RME96_HAS_ANALOG_OUT(rme96)) {
2234                 return -EINVAL;
2235         }
2236         spin_lock_irq(&rme96->lock);
2237         if (u->value.integer.value[0] != rme96->vol[0]) {
2238                 rme96->vol[0] = u->value.integer.value[0];
2239                 change = 1;
2240         }
2241         if (u->value.integer.value[1] != rme96->vol[1]) {
2242                 rme96->vol[1] = u->value.integer.value[1];
2243                 change = 1;
2244         }
2245         if (change) {
2246                 snd_rme96_apply_dac_volume(rme96);
2247         }
2248         spin_unlock_irq(&rme96->lock);
2249
2250         return change;
2251 }
2252
2253 static snd_kcontrol_new_t snd_rme96_controls[] = {
2254 {
2255         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2256         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2257         .info =         snd_rme96_control_spdif_info,
2258         .get =          snd_rme96_control_spdif_get,
2259         .put =          snd_rme96_control_spdif_put
2260 },
2261 {
2262         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2263         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2264         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2265         .info =         snd_rme96_control_spdif_stream_info,
2266         .get =          snd_rme96_control_spdif_stream_get,
2267         .put =          snd_rme96_control_spdif_stream_put
2268 },
2269 {
2270         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2271         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2272         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2273         .info =         snd_rme96_control_spdif_mask_info,
2274         .get =          snd_rme96_control_spdif_mask_get,
2275         .private_value = IEC958_AES0_NONAUDIO |
2276                         IEC958_AES0_PROFESSIONAL |
2277                         IEC958_AES0_CON_EMPHASIS
2278 },
2279 {
2280         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2281         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2282         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2283         .info =         snd_rme96_control_spdif_mask_info,
2284         .get =          snd_rme96_control_spdif_mask_get,
2285         .private_value = IEC958_AES0_NONAUDIO |
2286                         IEC958_AES0_PROFESSIONAL |
2287                         IEC958_AES0_PRO_EMPHASIS
2288 },
2289 {
2290         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2291         .name =         "Input Connector",
2292         .info =         snd_rme96_info_inputtype_control,
2293         .get =          snd_rme96_get_inputtype_control,
2294         .put =          snd_rme96_put_inputtype_control
2295 },
2296 {
2297         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2298         .name =         "Loopback Input",
2299         .info =         snd_rme96_info_loopback_control,
2300         .get =          snd_rme96_get_loopback_control,
2301         .put =          snd_rme96_put_loopback_control
2302 },
2303 {
2304         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2305         .name =         "Sample Clock Source",
2306         .info =         snd_rme96_info_clockmode_control,
2307         .get =          snd_rme96_get_clockmode_control,
2308         .put =          snd_rme96_put_clockmode_control
2309 },
2310 {
2311         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2312         .name =         "Monitor Tracks",
2313         .info =         snd_rme96_info_montracks_control,
2314         .get =          snd_rme96_get_montracks_control,
2315         .put =          snd_rme96_put_montracks_control
2316 },
2317 {
2318         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2319         .name =         "Attenuation",
2320         .info =         snd_rme96_info_attenuation_control,
2321         .get =          snd_rme96_get_attenuation_control,
2322         .put =          snd_rme96_put_attenuation_control
2323 },
2324 {
2325         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2326         .name =         "DAC Playback Volume",
2327         .info =         snd_rme96_dac_volume_info,
2328         .get =          snd_rme96_dac_volume_get,
2329         .put =          snd_rme96_dac_volume_put
2330 }
2331 };
2332
2333 static int
2334 snd_rme96_create_switches(snd_card_t *card,
2335                           rme96_t *rme96)
2336 {
2337         int idx, err;
2338         snd_kcontrol_t *kctl;
2339
2340         for (idx = 0; idx < 7; idx++) {
2341                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2342                         return err;
2343                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
2344                         rme96->spdif_ctl = kctl;
2345         }
2346
2347         if (RME96_HAS_ANALOG_OUT(rme96)) {
2348                 for (idx = 7; idx < 10; idx++)
2349                         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2350                                 return err;
2351         }
2352
2353         return 0;
2354 }
2355
2356 /*
2357  * Card initialisation
2358  */
2359
2360 static void snd_rme96_card_free(snd_card_t *card)
2361 {
2362         snd_rme96_free(card->private_data);
2363 }
2364
2365 static int __devinit
2366 snd_rme96_probe(struct pci_dev *pci,
2367                 const struct pci_device_id *pci_id)
2368 {
2369         static int dev;
2370         rme96_t *rme96;
2371         snd_card_t *card;
2372         int err;
2373         u8 val;
2374
2375         if (dev >= SNDRV_CARDS) {
2376                 return -ENODEV;
2377         }
2378         if (!enable[dev]) {
2379                 dev++;
2380                 return -ENOENT;
2381         }
2382         if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2383                                  sizeof(rme96_t))) == NULL)
2384                 return -ENOMEM;
2385         card->private_free = snd_rme96_card_free;
2386         rme96 = (rme96_t *)card->private_data;
2387         rme96->card = card;
2388         rme96->pci = pci;
2389         snd_card_set_dev(card, &pci->dev);
2390         if ((err = snd_rme96_create(rme96)) < 0) {
2391                 snd_card_free(card);
2392                 return err;
2393         }
2394
2395         strcpy(card->driver, "Digi96");
2396         switch (rme96->pci->device) {
2397         case PCI_DEVICE_ID_DIGI96:
2398                 strcpy(card->shortname, "RME Digi96");
2399                 break;
2400         case PCI_DEVICE_ID_DIGI96_8:
2401                 strcpy(card->shortname, "RME Digi96/8");
2402                 break;
2403         case PCI_DEVICE_ID_DIGI96_8_PRO:
2404                 strcpy(card->shortname, "RME Digi96/8 PRO");
2405                 break;
2406         case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2407                 pci_read_config_byte(rme96->pci, 8, &val);
2408                 if (val < 5) {
2409                         strcpy(card->shortname, "RME Digi96/8 PAD");
2410                 } else {
2411                         strcpy(card->shortname, "RME Digi96/8 PST");
2412                 }
2413                 break;
2414         }
2415         sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2416                 rme96->port, rme96->irq);
2417
2418         if ((err = snd_card_register(card)) < 0) {
2419                 snd_card_free(card);
2420                 return err;
2421         }
2422         pci_set_drvdata(pci, card);
2423         dev++;
2424         return 0;
2425 }
2426
2427 static void __devexit snd_rme96_remove(struct pci_dev *pci)
2428 {
2429         snd_card_free(pci_get_drvdata(pci));
2430         pci_set_drvdata(pci, NULL);
2431 }
2432
2433 static struct pci_driver driver = {
2434         .name = "RME Digi96",
2435         .id_table = snd_rme96_ids,
2436         .probe = snd_rme96_probe,
2437         .remove = __devexit_p(snd_rme96_remove),
2438 };
2439
2440 static int __init alsa_card_rme96_init(void)
2441 {
2442         return pci_register_driver(&driver);
2443 }
2444
2445 static void __exit alsa_card_rme96_exit(void)
2446 {
2447         pci_unregister_driver(&driver);
2448 }
2449
2450 module_init(alsa_card_rme96_init)
2451 module_exit(alsa_card_rme96_exit)