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   1 /*
   2  * C-Media CMI8788 driver - main driver module
   3  *
   4  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
   5  *
   6  *
   7  *  This driver is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License, version 2.
   9  *
  10  *  This driver is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this driver; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/mutex.h>
  23 #include <linux/pci.h>
  24 #include <sound/ac97_codec.h>
  25 #include <sound/asoundef.h>
  26 #include <sound/core.h>
  27 #include <sound/info.h>
  28 #include <sound/mpu401.h>
  29 #include <sound/pcm.h>
  30 #include "oxygen.h"
  31 #include "cm9780.h"
  32
  33 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  34 MODULE_DESCRIPTION("C-Media CMI8788 helper library");
  35 MODULE_LICENSE("GPL v2");
  36
  37 #define DRIVER "oxygen"
  38
  39 static inline int oxygen_uart_input_ready(struct oxygen *chip)
  40 {
  41         return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY);
  42 }
  43
  44 static void oxygen_read_uart(struct oxygen *chip)
  45 {
  46         if (unlikely(!oxygen_uart_input_ready(chip))) {
  47                 /* no data, but read it anyway to clear the interrupt */
  48                 oxygen_read8(chip, OXYGEN_MPU401);
  49                 return;
  50         }
  51         do {
  52                 u8 data = oxygen_read8(chip, OXYGEN_MPU401);
  53                 if (data == MPU401_ACK)
  54                         continue;
  55                 if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input))
  56                         chip->uart_input_count = 0;
  57                 chip->uart_input[chip->uart_input_count++] = data;
  58         } while (oxygen_uart_input_ready(chip));
  59         if (chip->model.uart_input)
  60                 chip->model.uart_input(chip);
  61 }
  62
  63 static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
  64 {
  65         struct oxygen *chip = dev_id;
  66         unsigned int status, clear, elapsed_streams, i;
  67
  68         status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
  69         if (!status)
  70                 return IRQ_NONE;
  71
  72         spin_lock(&chip->reg_lock);
  73
  74         clear = status & (OXYGEN_CHANNEL_A |
  75                           OXYGEN_CHANNEL_B |
  76                           OXYGEN_CHANNEL_C |
  77                           OXYGEN_CHANNEL_SPDIF |
  78                           OXYGEN_CHANNEL_MULTICH |
  79                           OXYGEN_CHANNEL_AC97 |
  80                           OXYGEN_INT_SPDIF_IN_DETECT |
  81                           OXYGEN_INT_GPIO |
  82                           OXYGEN_INT_AC97);
  83         if (clear) {
  84                 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
  85                         chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
  86                 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
  87                                chip->interrupt_mask & ~clear);
  88                 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
  89                                chip->interrupt_mask);
  90         }
  91
  92         elapsed_streams = status & chip->pcm_running;
  93
  94         spin_unlock(&chip->reg_lock);
  95
  96         for (i = 0; i < PCM_COUNT; ++i)
  97                 if ((elapsed_streams & (1 << i)) && chip->streams[i])
  98                         snd_pcm_period_elapsed(chip->streams[i]);
  99
 100         if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
 101                 spin_lock(&chip->reg_lock);
 102                 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
 103                 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
 104                          OXYGEN_SPDIF_RATE_INT)) {
 105                         /* write the interrupt bit(s) to clear */
 106                         oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
 107                         schedule_work(&chip->spdif_input_bits_work);
 108                 }
 109                 spin_unlock(&chip->reg_lock);
 110         }
 111
 112         if (status & OXYGEN_INT_GPIO)
 113                 schedule_work(&chip->gpio_work);
 114
 115         if (status & OXYGEN_INT_MIDI) {
 116                 if (chip->midi)
 117                         snd_mpu401_uart_interrupt(0, chip->midi->private_data);
 118                 else
 119                         oxygen_read_uart(chip);
 120         }
 121
 122         if (status & OXYGEN_INT_AC97)
 123                 wake_up(&chip->ac97_waitqueue);
 124
 125         return IRQ_HANDLED;
 126 }
 127
 128 static void oxygen_spdif_input_bits_changed(struct work_struct *work)
 129 {
 130         struct oxygen *chip = container_of(work, struct oxygen,
 131                                            spdif_input_bits_work);
 132         u32 reg;
 133
 134         /*
 135          * This function gets called when there is new activity on the SPDIF
 136          * input, or when we lose lock on the input signal, or when the rate
 137          * changes.
 138          */
 139         msleep(1);
 140         spin_lock_irq(&chip->reg_lock);
 141         reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
 142         if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
 143                     OXYGEN_SPDIF_LOCK_STATUS))
 144             == OXYGEN_SPDIF_SENSE_STATUS) {
 145                 /*
 146                  * If we detect activity on the SPDIF input but cannot lock to
 147                  * a signal, the clock bit is likely to be wrong.
 148                  */
 149                 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
 150                 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
 151                 spin_unlock_irq(&chip->reg_lock);
 152                 msleep(1);
 153                 spin_lock_irq(&chip->reg_lock);
 154                 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
 155                 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
 156                             OXYGEN_SPDIF_LOCK_STATUS))
 157                     == OXYGEN_SPDIF_SENSE_STATUS) {
 158                         /* nothing detected with either clock; give up */
 159                         if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
 160                             == OXYGEN_SPDIF_IN_CLOCK_192) {
 161                                 /*
 162                                  * Reset clock to <= 96 kHz because this is
 163                                  * more likely to be received next time.
 164                                  */
 165                                 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
 166                                 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
 167                                 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
 168                         }
 169                 }
 170         }
 171         spin_unlock_irq(&chip->reg_lock);
 172
 173         if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
 174                 spin_lock_irq(&chip->reg_lock);
 175                 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
 176                 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
 177                                chip->interrupt_mask);
 178                 spin_unlock_irq(&chip->reg_lock);
 179
 180                 /*
 181                  * We don't actually know that any channel status bits have
 182                  * changed, but let's send a notification just to be sure.
 183                  */
 184                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
 185                                &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
 186         }
 187 }
 188
 189 static void oxygen_gpio_changed(struct work_struct *work)
 190 {
 191         struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
 192
 193         if (chip->model.gpio_changed)
 194                 chip->model.gpio_changed(chip);
 195 }
 196
 197 #ifdef CONFIG_PROC_FS
 198 static void oxygen_proc_read(struct snd_info_entry *entry,
 199                              struct snd_info_buffer *buffer)
 200 {
 201         struct oxygen *chip = entry->private_data;
 202         int i, j;
 203
 204         snd_iprintf(buffer, "CMI8788\n\n");
 205         for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
 206                 snd_iprintf(buffer, "%02x:", i);
 207                 for (j = 0; j < 0x10; ++j)
 208                         snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
 209                 snd_iprintf(buffer, "\n");
 210         }
 211         if (mutex_lock_interruptible(&chip->mutex) < 0)
 212                 return;
 213         if (chip->has_ac97_0) {
 214                 snd_iprintf(buffer, "\nAC97\n");
 215                 for (i = 0; i < 0x80; i += 0x10) {
 216                         snd_iprintf(buffer, "%02x:", i);
 217                         for (j = 0; j < 0x10; j += 2)
 218                                 snd_iprintf(buffer, " %04x",
 219                                             oxygen_read_ac97(chip, 0, i + j));
 220                         snd_iprintf(buffer, "\n");
 221                 }
 222         }
 223         if (chip->has_ac97_1) {
 224                 snd_iprintf(buffer, "\nAC97 2\n");
 225                 for (i = 0; i < 0x80; i += 0x10) {
 226                         snd_iprintf(buffer, "%02x:", i);
 227                         for (j = 0; j < 0x10; j += 2)
 228                                 snd_iprintf(buffer, " %04x",
 229                                             oxygen_read_ac97(chip, 1, i + j));
 230                         snd_iprintf(buffer, "\n");
 231                 }
 232         }
 233         mutex_unlock(&chip->mutex);
 234 }
 235
 236 static void oxygen_proc_init(struct oxygen *chip)
 237 {
 238         struct snd_info_entry *entry;
 239
 240         if (!snd_card_proc_new(chip->card, "cmi8788", &entry))
 241                 snd_info_set_text_ops(entry, chip, oxygen_proc_read);
 242 }
 243 #else
 244 #define oxygen_proc_init(chip)
 245 #endif
 246
 247 static const struct pci_device_id *
 248 oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[])
 249 {
 250         u16 subdevice;
 251
 252         /*
 253          * Make sure the EEPROM pins are available, i.e., not used for SPI.
 254          * (This function is called before we initialize or use SPI.)
 255          */
 256         oxygen_clear_bits8(chip, OXYGEN_FUNCTION,
 257                            OXYGEN_FUNCTION_ENABLE_SPI_4_5);
 258         /*
 259          * Read the subsystem device ID directly from the EEPROM, because the
 260          * chip didn't if the first EEPROM word was overwritten.
 261          */
 262         subdevice = oxygen_read_eeprom(chip, 2);
 263         /*
 264          * We use only the subsystem device ID for searching because it is
 265          * unique even without the subsystem vendor ID, which may have been
 266          * overwritten in the EEPROM.
 267          */
 268         for (; ids->vendor; ++ids)
 269                 if (ids->subdevice == subdevice &&
 270                     ids->driver_data != BROKEN_EEPROM_DRIVER_DATA)
 271                         return ids;
 272         return NULL;
 273 }
 274
 275 static void oxygen_init(struct oxygen *chip)
 276 {
 277         unsigned int i;
 278
 279         chip->dac_routing = 1;
 280         for (i = 0; i < 8; ++i)
 281                 chip->dac_volume[i] = chip->model.dac_volume_min;
 282         chip->dac_mute = 1;
 283         chip->spdif_playback_enable = 1;
 284         chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
 285                 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
 286         chip->spdif_pcm_bits = chip->spdif_bits;
 287
 288         if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)
 289                 chip->revision = 2;
 290         else
 291                 chip->revision = 1;
 292
 293         if (chip->revision == 1)
 294                 oxygen_set_bits8(chip, OXYGEN_MISC,
 295                                  OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
 296
 297         i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
 298         chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
 299         chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
 300
 301         oxygen_write8_masked(chip, OXYGEN_FUNCTION,
 302                              OXYGEN_FUNCTION_RESET_CODEC |
 303                              chip->model.function_flags,
 304                              OXYGEN_FUNCTION_RESET_CODEC |
 305                              OXYGEN_FUNCTION_2WIRE_SPI_MASK |
 306                              OXYGEN_FUNCTION_ENABLE_SPI_4_5);
 307         oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
 308         oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
 309         oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
 310                       OXYGEN_PLAY_CHANNELS_2 |
 311                       OXYGEN_DMA_A_BURST_8 |
 312                       OXYGEN_DMA_MULTICH_BURST_8);
 313         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
 314         oxygen_write8_masked(chip, OXYGEN_MISC,
 315                              chip->model.misc_flags,
 316                              OXYGEN_MISC_WRITE_PCI_SUBID |
 317                              OXYGEN_MISC_REC_C_FROM_SPDIF |
 318                              OXYGEN_MISC_REC_B_FROM_AC97 |
 319                              OXYGEN_MISC_REC_A_FROM_MULTICH |
 320                              OXYGEN_MISC_MIDI);
 321         oxygen_write8(chip, OXYGEN_REC_FORMAT,
 322                       (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
 323                       (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
 324                       (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
 325         oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
 326                       (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
 327                       (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
 328         oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
 329         oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
 330                        OXYGEN_RATE_48000 | chip->model.dac_i2s_format |
 331                        OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
 332                        OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
 333         if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
 334                 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
 335                                OXYGEN_RATE_48000 | chip->model.adc_i2s_format |
 336                                OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
 337                                OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
 338         else
 339                 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
 340                                OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
 341         if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 |
 342                                          CAPTURE_2_FROM_I2S_2))
 343                 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
 344                                OXYGEN_RATE_48000 | chip->model.adc_i2s_format |
 345                                OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
 346                                OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
 347         else
 348                 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
 349                                OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
 350         oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
 351                        OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
 352         oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
 353                             OXYGEN_SPDIF_OUT_ENABLE |
 354                             OXYGEN_SPDIF_LOOPBACK);
 355         if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
 356                 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
 357                                       OXYGEN_SPDIF_SENSE_MASK |
 358                                       OXYGEN_SPDIF_LOCK_MASK |
 359                                       OXYGEN_SPDIF_RATE_MASK |
 360                                       OXYGEN_SPDIF_LOCK_PAR |
 361                                       OXYGEN_SPDIF_IN_CLOCK_96,
 362                                       OXYGEN_SPDIF_SENSE_MASK |
 363                                       OXYGEN_SPDIF_LOCK_MASK |
 364                                       OXYGEN_SPDIF_RATE_MASK |
 365                                       OXYGEN_SPDIF_SENSE_PAR |
 366                                       OXYGEN_SPDIF_LOCK_PAR |
 367                                       OXYGEN_SPDIF_IN_CLOCK_MASK);
 368         else
 369                 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
 370                                     OXYGEN_SPDIF_SENSE_MASK |
 371                                     OXYGEN_SPDIF_LOCK_MASK |
 372                                     OXYGEN_SPDIF_RATE_MASK);
 373         oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
 374         oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
 375                        OXYGEN_2WIRE_LENGTH_8 |
 376                        OXYGEN_2WIRE_INTERRUPT_MASK |
 377                        OXYGEN_2WIRE_SPEED_STANDARD);
 378         oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
 379         oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
 380         oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
 381         oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
 382                        OXYGEN_PLAY_MULTICH_I2S_DAC |
 383                        OXYGEN_PLAY_SPDIF_SPDIF |
 384                        (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
 385                        (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
 386                        (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
 387                        (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
 388         oxygen_write8(chip, OXYGEN_REC_ROUTING,
 389                       OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
 390                       OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
 391                       OXYGEN_REC_C_ROUTE_SPDIF);
 392         oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
 393         oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
 394                       (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
 395                       (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
 396                       (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
 397                       (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
 398
 399         if (chip->has_ac97_0 | chip->has_ac97_1)
 400                 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
 401                               OXYGEN_AC97_INT_READ_DONE |
 402                               OXYGEN_AC97_INT_WRITE_DONE);
 403         else
 404                 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
 405         oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
 406         oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
 407         if (!(chip->has_ac97_0 | chip->has_ac97_1))
 408                 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
 409                                   OXYGEN_AC97_CLOCK_DISABLE);
 410         if (!chip->has_ac97_0) {
 411                 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
 412                                   OXYGEN_AC97_NO_CODEC_0);
 413         } else {
 414                 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
 415                 msleep(1);
 416                 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
 417                                      CM9780_GPIO0IO | CM9780_GPIO1IO);
 418                 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
 419                                      CM9780_BSTSEL | CM9780_STRO_MIC |
 420                                      CM9780_MIX2FR | CM9780_PCBSW);
 421                 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
 422                                      CM9780_RSOE | CM9780_CBOE |
 423                                      CM9780_SSOE | CM9780_FROE |
 424                                      CM9780_MIC2MIC | CM9780_LI2LI);
 425                 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
 426                 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
 427                 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
 428                 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
 429                 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
 430                 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
 431                 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
 432                 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
 433                 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
 434                 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
 435                 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
 436                                        CM9780_GPO0);
 437                 /* power down unused ADCs and DACs */
 438                 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
 439                                      AC97_PD_PR0 | AC97_PD_PR1);
 440                 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
 441                                      AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
 442         }
 443         if (chip->has_ac97_1) {
 444                 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
 445                                   OXYGEN_AC97_CODEC1_SLOT3 |
 446                                   OXYGEN_AC97_CODEC1_SLOT4);
 447                 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
 448                 msleep(1);
 449                 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
 450                 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
 451                 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
 452                 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
 453                 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
 454                 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
 455                 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
 456                 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
 457                 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
 458                 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
 459                 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
 460                 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
 461         }
 462 }
 463
 464 static void oxygen_card_free(struct snd_card *card)
 465 {
 466         struct oxygen *chip = card->private_data;
 467
 468         spin_lock_irq(&chip->reg_lock);
 469         chip->interrupt_mask = 0;
 470         chip->pcm_running = 0;
 471         oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
 472         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
 473         spin_unlock_irq(&chip->reg_lock);
 474         if (chip->irq >= 0)
 475                 free_irq(chip->irq, chip);
 476         flush_scheduled_work();
 477         chip->model.cleanup(chip);
 478         kfree(chip->model_data);
 479         mutex_destroy(&chip->mutex);
 480         pci_release_regions(chip->pci);
 481         pci_disable_device(chip->pci);
 482 }
 483
 484 int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
 485                      struct module *owner,
 486                      const struct pci_device_id *ids,
 487                      int (*get_model)(struct oxygen *chip,
 488                                       const struct pci_device_id *id
 489                                      )
 490                     )
 491 {
 492         struct snd_card *card;
 493         struct oxygen *chip;
 494         const struct pci_device_id *pci_id;
 495         int err;
 496
 497         err = snd_card_create(index, id, owner, sizeof(*chip), &card);
 498         if (err < 0)
 499                 return err;
 500
 501         chip = card->private_data;
 502         chip->card = card;
 503         chip->pci = pci;
 504         chip->irq = -1;
 505         spin_lock_init(&chip->reg_lock);
 506         mutex_init(&chip->mutex);
 507         INIT_WORK(&chip->spdif_input_bits_work,
 508                   oxygen_spdif_input_bits_changed);
 509         INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
 510         init_waitqueue_head(&chip->ac97_waitqueue);
 511
 512         err = pci_enable_device(pci);
 513         if (err < 0)
 514                 goto err_card;
 515
 516         err = pci_request_regions(pci, DRIVER);
 517         if (err < 0) {
 518                 snd_printk(KERN_ERR "cannot reserve PCI resources\n");
 519                 goto err_pci_enable;
 520         }
 521
 522         if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
 523             pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
 524                 snd_printk(KERN_ERR "invalid PCI I/O range\n");
 525                 err = -ENXIO;
 526                 goto err_pci_regions;
 527         }
 528         chip->addr = pci_resource_start(pci, 0);
 529
 530         pci_id = oxygen_search_pci_id(chip, ids);
 531         if (!pci_id) {
 532                 err = -ENODEV;
 533                 goto err_pci_regions;
 534         }
 535         err = get_model(chip, pci_id);
 536         if (err < 0)
 537                 goto err_pci_regions;
 538
 539         if (chip->model.model_data_size) {
 540                 chip->model_data = kmalloc(chip->model.model_data_size,
 541                                            GFP_KERNEL);
 542                 if (!chip->model_data) {
 543                         err = -ENOMEM;
 544                         goto err_pci_regions;
 545                 }
 546         }
 547
 548         pci_set_master(pci);
 549         snd_card_set_dev(card, &pci->dev);
 550         card->private_free = oxygen_card_free;
 551
 552         oxygen_init(chip);
 553         chip->model.init(chip);
 554
 555         err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
 556                           DRIVER, chip);
 557         if (err < 0) {
 558                 snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
 559                 goto err_card;
 560         }
 561         chip->irq = pci->irq;
 562
 563         strcpy(card->driver, chip->model.chip);
 564         strcpy(card->shortname, chip->model.shortname);
 565         sprintf(card->longname, "%s (rev %u) at %#lx, irq %i",
 566                 chip->model.longname, chip->revision, chip->addr, chip->irq);
 567         strcpy(card->mixername, chip->model.chip);
 568         snd_component_add(card, chip->model.chip);
 569
 570         err = oxygen_pcm_init(chip);
 571         if (err < 0)
 572                 goto err_card;
 573
 574         err = oxygen_mixer_init(chip);
 575         if (err < 0)
 576                 goto err_card;
 577
 578         if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) {
 579                 unsigned int info_flags = MPU401_INFO_INTEGRATED;
 580                 if (chip->model.device_config & MIDI_OUTPUT)
 581                         info_flags |= MPU401_INFO_OUTPUT;
 582                 if (chip->model.device_config & MIDI_INPUT)
 583                         info_flags |= MPU401_INFO_INPUT;
 584                 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
 585                                           chip->addr + OXYGEN_MPU401,
 586                                           info_flags, 0, 0,
 587                                           &chip->midi);
 588                 if (err < 0)
 589                         goto err_card;
 590         }
 591
 592         oxygen_proc_init(chip);
 593
 594         spin_lock_irq(&chip->reg_lock);
 595         if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
 596                 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
 597         if (chip->has_ac97_0 | chip->has_ac97_1)
 598                 chip->interrupt_mask |= OXYGEN_INT_AC97;
 599         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
 600         spin_unlock_irq(&chip->reg_lock);
 601
 602         err = snd_card_register(card);
 603         if (err < 0)
 604                 goto err_card;
 605
 606         pci_set_drvdata(pci, card);
 607         return 0;
 608
 609 err_pci_regions:
 610         pci_release_regions(pci);
 611 err_pci_enable:
 612         pci_disable_device(pci);
 613 err_card:
 614         snd_card_free(card);
 615         return err;
 616 }
 617 EXPORT_SYMBOL(oxygen_pci_probe);
 618
 619 void oxygen_pci_remove(struct pci_dev *pci)
 620 {
 621         snd_card_free(pci_get_drvdata(pci));
 622         pci_set_drvdata(pci, NULL);
 623 }
 624 EXPORT_SYMBOL(oxygen_pci_remove);
 625
 626 #ifdef CONFIG_PM
 627 int oxygen_pci_suspend(struct pci_dev *pci, pm_message_t state)
 628 {
 629         struct snd_card *card = pci_get_drvdata(pci);
 630         struct oxygen *chip = card->private_data;
 631         unsigned int i, saved_interrupt_mask;
 632
 633         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 634
 635         for (i = 0; i < PCM_COUNT; ++i)
 636                 if (chip->streams[i])
 637                         snd_pcm_suspend(chip->streams[i]);
 638
 639         if (chip->model.suspend)
 640                 chip->model.suspend(chip);
 641
 642         spin_lock_irq(&chip->reg_lock);
 643         saved_interrupt_mask = chip->interrupt_mask;
 644         chip->interrupt_mask = 0;
 645         oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
 646         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
 647         spin_unlock_irq(&chip->reg_lock);
 648
 649         synchronize_irq(chip->irq);
 650         flush_scheduled_work();
 651         chip->interrupt_mask = saved_interrupt_mask;
 652
 653         pci_disable_device(pci);
 654         pci_save_state(pci);
 655         pci_set_power_state(pci, pci_choose_state(pci, state));
 656         return 0;
 657 }
 658 EXPORT_SYMBOL(oxygen_pci_suspend);
 659
 660 static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
 661         0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
 662         0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
 663 };
 664 static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
 665         { 0x18284fa2, 0x03060000 },
 666         { 0x00007fa6, 0x00200000 }
 667 };
 668
 669 static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
 670 {
 671         return bitmap[bit / 32] & (1 << (bit & 31));
 672 }
 673
 674 static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
 675 {
 676         unsigned int i;
 677
 678         oxygen_write_ac97(chip, codec, AC97_RESET, 0);
 679         msleep(1);
 680         for (i = 1; i < 0x40; ++i)
 681                 if (is_bit_set(ac97_registers_to_restore[codec], i))
 682                         oxygen_write_ac97(chip, codec, i * 2,
 683                                           chip->saved_ac97_registers[codec][i]);
 684 }
 685
 686 int oxygen_pci_resume(struct pci_dev *pci)
 687 {
 688         struct snd_card *card = pci_get_drvdata(pci);
 689         struct oxygen *chip = card->private_data;
 690         unsigned int i;
 691
 692         pci_set_power_state(pci, PCI_D0);
 693         pci_restore_state(pci);
 694         if (pci_enable_device(pci) < 0) {
 695                 snd_printk(KERN_ERR "cannot reenable device");
 696                 snd_card_disconnect(card);
 697                 return -EIO;
 698         }
 699         pci_set_master(pci);
 700
 701         oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
 702         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
 703         for (i = 0; i < OXYGEN_IO_SIZE; ++i)
 704                 if (is_bit_set(registers_to_restore, i))
 705                         oxygen_write8(chip, i, chip->saved_registers._8[i]);
 706         if (chip->has_ac97_0)
 707                 oxygen_restore_ac97(chip, 0);
 708         if (chip->has_ac97_1)
 709                 oxygen_restore_ac97(chip, 1);
 710
 711         if (chip->model.resume)
 712                 chip->model.resume(chip);
 713
 714         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
 715
 716         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 717         return 0;
 718 }
 719 EXPORT_SYMBOL(oxygen_pci_resume);
 720 #endif /* CONFIG_PM */