2 * C-Media CMI8788 driver - main driver module
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/mutex.h>
23 #include <linux/pci.h>
24 #include <sound/ac97_codec.h>
25 #include <sound/asoundef.h>
26 #include <sound/core.h>
27 #include <sound/info.h>
28 #include <sound/mpu401.h>
29 #include <sound/pcm.h>
33 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
34 MODULE_DESCRIPTION("C-Media CMI8788 helper library");
35 MODULE_LICENSE("GPL v2");
37 #define DRIVER "oxygen"
39 static inline int oxygen_uart_input_ready(struct oxygen *chip)
41 return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY);
44 static void oxygen_read_uart(struct oxygen *chip)
46 if (unlikely(!oxygen_uart_input_ready(chip))) {
47 /* no data, but read it anyway to clear the interrupt */
48 oxygen_read8(chip, OXYGEN_MPU401);
52 u8 data = oxygen_read8(chip, OXYGEN_MPU401);
53 if (data == MPU401_ACK)
55 if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input))
56 chip->uart_input_count = 0;
57 chip->uart_input[chip->uart_input_count++] = data;
58 } while (oxygen_uart_input_ready(chip));
59 if (chip->model.uart_input)
60 chip->model.uart_input(chip);
63 static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
65 struct oxygen *chip = dev_id;
66 unsigned int status, clear, elapsed_streams, i;
68 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
72 spin_lock(&chip->reg_lock);
74 clear = status & (OXYGEN_CHANNEL_A |
77 OXYGEN_CHANNEL_SPDIF |
78 OXYGEN_CHANNEL_MULTICH |
80 OXYGEN_INT_SPDIF_IN_DETECT |
84 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
85 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
86 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
87 chip->interrupt_mask & ~clear);
88 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
89 chip->interrupt_mask);
92 elapsed_streams = status & chip->pcm_running;
94 spin_unlock(&chip->reg_lock);
96 for (i = 0; i < PCM_COUNT; ++i)
97 if ((elapsed_streams & (1 << i)) && chip->streams[i])
98 snd_pcm_period_elapsed(chip->streams[i]);
100 if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
101 spin_lock(&chip->reg_lock);
102 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
103 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
104 OXYGEN_SPDIF_RATE_INT)) {
105 /* write the interrupt bit(s) to clear */
106 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
107 schedule_work(&chip->spdif_input_bits_work);
109 spin_unlock(&chip->reg_lock);
112 if (status & OXYGEN_INT_GPIO)
113 schedule_work(&chip->gpio_work);
115 if (status & OXYGEN_INT_MIDI) {
117 snd_mpu401_uart_interrupt(0, chip->midi->private_data);
119 oxygen_read_uart(chip);
122 if (status & OXYGEN_INT_AC97)
123 wake_up(&chip->ac97_waitqueue);
128 static void oxygen_spdif_input_bits_changed(struct work_struct *work)
130 struct oxygen *chip = container_of(work, struct oxygen,
131 spdif_input_bits_work);
135 * This function gets called when there is new activity on the SPDIF
136 * input, or when we lose lock on the input signal, or when the rate
140 spin_lock_irq(&chip->reg_lock);
141 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
142 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
143 OXYGEN_SPDIF_LOCK_STATUS))
144 == OXYGEN_SPDIF_SENSE_STATUS) {
146 * If we detect activity on the SPDIF input but cannot lock to
147 * a signal, the clock bit is likely to be wrong.
149 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
150 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
151 spin_unlock_irq(&chip->reg_lock);
153 spin_lock_irq(&chip->reg_lock);
154 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
155 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
156 OXYGEN_SPDIF_LOCK_STATUS))
157 == OXYGEN_SPDIF_SENSE_STATUS) {
158 /* nothing detected with either clock; give up */
159 if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
160 == OXYGEN_SPDIF_IN_CLOCK_192) {
162 * Reset clock to <= 96 kHz because this is
163 * more likely to be received next time.
165 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
166 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
167 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
171 spin_unlock_irq(&chip->reg_lock);
173 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
174 spin_lock_irq(&chip->reg_lock);
175 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
176 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
177 chip->interrupt_mask);
178 spin_unlock_irq(&chip->reg_lock);
181 * We don't actually know that any channel status bits have
182 * changed, but let's send a notification just to be sure.
184 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
185 &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
189 static void oxygen_gpio_changed(struct work_struct *work)
191 struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
193 if (chip->model.gpio_changed)
194 chip->model.gpio_changed(chip);
197 #ifdef CONFIG_PROC_FS
198 static void oxygen_proc_read(struct snd_info_entry *entry,
199 struct snd_info_buffer *buffer)
201 struct oxygen *chip = entry->private_data;
204 snd_iprintf(buffer, "CMI8788\n\n");
205 for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
206 snd_iprintf(buffer, "%02x:", i);
207 for (j = 0; j < 0x10; ++j)
208 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
209 snd_iprintf(buffer, "\n");
211 if (mutex_lock_interruptible(&chip->mutex) < 0)
213 if (chip->has_ac97_0) {
214 snd_iprintf(buffer, "\nAC97\n");
215 for (i = 0; i < 0x80; i += 0x10) {
216 snd_iprintf(buffer, "%02x:", i);
217 for (j = 0; j < 0x10; j += 2)
218 snd_iprintf(buffer, " %04x",
219 oxygen_read_ac97(chip, 0, i + j));
220 snd_iprintf(buffer, "\n");
223 if (chip->has_ac97_1) {
224 snd_iprintf(buffer, "\nAC97 2\n");
225 for (i = 0; i < 0x80; i += 0x10) {
226 snd_iprintf(buffer, "%02x:", i);
227 for (j = 0; j < 0x10; j += 2)
228 snd_iprintf(buffer, " %04x",
229 oxygen_read_ac97(chip, 1, i + j));
230 snd_iprintf(buffer, "\n");
233 mutex_unlock(&chip->mutex);
236 static void oxygen_proc_init(struct oxygen *chip)
238 struct snd_info_entry *entry;
240 if (!snd_card_proc_new(chip->card, "cmi8788", &entry))
241 snd_info_set_text_ops(entry, chip, oxygen_proc_read);
244 #define oxygen_proc_init(chip)
247 static void oxygen_init(struct oxygen *chip)
251 chip->dac_routing = 1;
252 for (i = 0; i < 8; ++i)
253 chip->dac_volume[i] = chip->model.dac_volume_min;
255 chip->spdif_playback_enable = 1;
256 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
257 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
258 chip->spdif_pcm_bits = chip->spdif_bits;
260 if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)
265 if (chip->revision == 1)
266 oxygen_set_bits8(chip, OXYGEN_MISC,
267 OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
269 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
270 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
271 chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
273 oxygen_write8_masked(chip, OXYGEN_FUNCTION,
274 OXYGEN_FUNCTION_RESET_CODEC |
275 chip->model.function_flags,
276 OXYGEN_FUNCTION_RESET_CODEC |
277 OXYGEN_FUNCTION_2WIRE_SPI_MASK |
278 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
279 oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
280 oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
281 oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
282 OXYGEN_PLAY_CHANNELS_2 |
283 OXYGEN_DMA_A_BURST_8 |
284 OXYGEN_DMA_MULTICH_BURST_8);
285 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
286 oxygen_write8_masked(chip, OXYGEN_MISC,
287 chip->model.misc_flags,
288 OXYGEN_MISC_WRITE_PCI_SUBID |
289 OXYGEN_MISC_REC_C_FROM_SPDIF |
290 OXYGEN_MISC_REC_B_FROM_AC97 |
291 OXYGEN_MISC_REC_A_FROM_MULTICH |
293 oxygen_write8(chip, OXYGEN_REC_FORMAT,
294 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
295 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
296 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
297 oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
298 (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
299 (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
300 oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
301 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
302 OXYGEN_RATE_48000 | chip->model.dac_i2s_format |
303 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
304 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
305 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
306 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
307 OXYGEN_RATE_48000 | chip->model.adc_i2s_format |
308 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
309 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
311 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
312 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
313 if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 |
314 CAPTURE_2_FROM_I2S_2))
315 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
316 OXYGEN_RATE_48000 | chip->model.adc_i2s_format |
317 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
318 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
320 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
321 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
322 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
323 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
324 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
325 OXYGEN_SPDIF_OUT_ENABLE |
326 OXYGEN_SPDIF_LOOPBACK);
327 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
328 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
329 OXYGEN_SPDIF_SENSE_MASK |
330 OXYGEN_SPDIF_LOCK_MASK |
331 OXYGEN_SPDIF_RATE_MASK |
332 OXYGEN_SPDIF_LOCK_PAR |
333 OXYGEN_SPDIF_IN_CLOCK_96,
334 OXYGEN_SPDIF_SENSE_MASK |
335 OXYGEN_SPDIF_LOCK_MASK |
336 OXYGEN_SPDIF_RATE_MASK |
337 OXYGEN_SPDIF_SENSE_PAR |
338 OXYGEN_SPDIF_LOCK_PAR |
339 OXYGEN_SPDIF_IN_CLOCK_MASK);
341 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
342 OXYGEN_SPDIF_SENSE_MASK |
343 OXYGEN_SPDIF_LOCK_MASK |
344 OXYGEN_SPDIF_RATE_MASK);
345 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
346 oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
347 OXYGEN_2WIRE_LENGTH_8 |
348 OXYGEN_2WIRE_INTERRUPT_MASK |
349 OXYGEN_2WIRE_SPEED_STANDARD);
350 oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
351 oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
352 oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
353 oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
354 OXYGEN_PLAY_MULTICH_I2S_DAC |
355 OXYGEN_PLAY_SPDIF_SPDIF |
356 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
357 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
358 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
359 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
360 oxygen_write8(chip, OXYGEN_REC_ROUTING,
361 OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
362 OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
363 OXYGEN_REC_C_ROUTE_SPDIF);
364 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
365 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
366 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
367 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
368 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
369 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
371 if (chip->has_ac97_0 | chip->has_ac97_1)
372 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
373 OXYGEN_AC97_INT_READ_DONE |
374 OXYGEN_AC97_INT_WRITE_DONE);
376 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
377 oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
378 oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
379 if (!(chip->has_ac97_0 | chip->has_ac97_1))
380 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
381 OXYGEN_AC97_CLOCK_DISABLE);
382 if (!chip->has_ac97_0) {
383 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
384 OXYGEN_AC97_NO_CODEC_0);
386 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
388 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
389 CM9780_GPIO0IO | CM9780_GPIO1IO);
390 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
391 CM9780_BSTSEL | CM9780_STRO_MIC |
392 CM9780_MIX2FR | CM9780_PCBSW);
393 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
394 CM9780_RSOE | CM9780_CBOE |
395 CM9780_SSOE | CM9780_FROE |
396 CM9780_MIC2MIC | CM9780_LI2LI);
397 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
398 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
399 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
400 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
401 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
402 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
403 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
404 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
405 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
406 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
407 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
409 /* power down unused ADCs and DACs */
410 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
411 AC97_PD_PR0 | AC97_PD_PR1);
412 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
413 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
415 if (chip->has_ac97_1) {
416 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
417 OXYGEN_AC97_CODEC1_SLOT3 |
418 OXYGEN_AC97_CODEC1_SLOT4);
419 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
421 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
422 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
423 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
424 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
425 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
426 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
427 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
428 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
429 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
430 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
431 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
432 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
436 static void oxygen_card_free(struct snd_card *card)
438 struct oxygen *chip = card->private_data;
440 spin_lock_irq(&chip->reg_lock);
441 chip->interrupt_mask = 0;
442 chip->pcm_running = 0;
443 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
444 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
445 spin_unlock_irq(&chip->reg_lock);
447 free_irq(chip->irq, chip);
448 flush_scheduled_work();
449 chip->model.cleanup(chip);
450 kfree(chip->model_data);
451 mutex_destroy(&chip->mutex);
452 pci_release_regions(chip->pci);
453 pci_disable_device(chip->pci);
456 int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
457 struct module *owner,
458 const struct oxygen_model *model,
459 unsigned long driver_data)
461 struct snd_card *card;
465 err = snd_card_create(index, id, owner, sizeof(*chip), &card);
469 chip = card->private_data;
473 chip->model = *model;
474 spin_lock_init(&chip->reg_lock);
475 mutex_init(&chip->mutex);
476 INIT_WORK(&chip->spdif_input_bits_work,
477 oxygen_spdif_input_bits_changed);
478 INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
479 init_waitqueue_head(&chip->ac97_waitqueue);
481 err = pci_enable_device(pci);
485 err = pci_request_regions(pci, DRIVER);
487 snd_printk(KERN_ERR "cannot reserve PCI resources\n");
491 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
492 pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
493 snd_printk(KERN_ERR "invalid PCI I/O range\n");
495 goto err_pci_regions;
497 chip->addr = pci_resource_start(pci, 0);
499 if (chip->model.model_data_size) {
500 chip->model_data = kmalloc(chip->model.model_data_size,
502 if (!chip->model_data) {
504 goto err_pci_regions;
509 snd_card_set_dev(card, &pci->dev);
510 card->private_free = oxygen_card_free;
512 if (chip->model.probe) {
513 err = chip->model.probe(chip, driver_data);
518 chip->model.init(chip);
520 err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
523 snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
526 chip->irq = pci->irq;
528 strcpy(card->driver, chip->model.chip);
529 strcpy(card->shortname, chip->model.shortname);
530 sprintf(card->longname, "%s (rev %u) at %#lx, irq %i",
531 chip->model.longname, chip->revision, chip->addr, chip->irq);
532 strcpy(card->mixername, chip->model.chip);
533 snd_component_add(card, chip->model.chip);
535 err = oxygen_pcm_init(chip);
539 err = oxygen_mixer_init(chip);
543 if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) {
544 unsigned int info_flags = MPU401_INFO_INTEGRATED;
545 if (chip->model.device_config & MIDI_OUTPUT)
546 info_flags |= MPU401_INFO_OUTPUT;
547 if (chip->model.device_config & MIDI_INPUT)
548 info_flags |= MPU401_INFO_INPUT;
549 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
550 chip->addr + OXYGEN_MPU401,
557 oxygen_proc_init(chip);
559 spin_lock_irq(&chip->reg_lock);
560 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
561 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
562 if (chip->has_ac97_0 | chip->has_ac97_1)
563 chip->interrupt_mask |= OXYGEN_INT_AC97;
564 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
565 spin_unlock_irq(&chip->reg_lock);
567 err = snd_card_register(card);
571 pci_set_drvdata(pci, card);
575 pci_release_regions(pci);
577 pci_disable_device(pci);
582 EXPORT_SYMBOL(oxygen_pci_probe);
584 void oxygen_pci_remove(struct pci_dev *pci)
586 snd_card_free(pci_get_drvdata(pci));
587 pci_set_drvdata(pci, NULL);
589 EXPORT_SYMBOL(oxygen_pci_remove);
592 int oxygen_pci_suspend(struct pci_dev *pci, pm_message_t state)
594 struct snd_card *card = pci_get_drvdata(pci);
595 struct oxygen *chip = card->private_data;
596 unsigned int i, saved_interrupt_mask;
598 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
600 for (i = 0; i < PCM_COUNT; ++i)
601 if (chip->streams[i])
602 snd_pcm_suspend(chip->streams[i]);
604 if (chip->model.suspend)
605 chip->model.suspend(chip);
607 spin_lock_irq(&chip->reg_lock);
608 saved_interrupt_mask = chip->interrupt_mask;
609 chip->interrupt_mask = 0;
610 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
611 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
612 spin_unlock_irq(&chip->reg_lock);
614 synchronize_irq(chip->irq);
615 flush_scheduled_work();
616 chip->interrupt_mask = saved_interrupt_mask;
618 pci_disable_device(pci);
620 pci_set_power_state(pci, pci_choose_state(pci, state));
623 EXPORT_SYMBOL(oxygen_pci_suspend);
625 static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
626 0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
627 0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
629 static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
630 { 0x18284fa2, 0x03060000 },
631 { 0x00007fa6, 0x00200000 }
634 static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
636 return bitmap[bit / 32] & (1 << (bit & 31));
639 static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
643 oxygen_write_ac97(chip, codec, AC97_RESET, 0);
645 for (i = 1; i < 0x40; ++i)
646 if (is_bit_set(ac97_registers_to_restore[codec], i))
647 oxygen_write_ac97(chip, codec, i * 2,
648 chip->saved_ac97_registers[codec][i]);
651 int oxygen_pci_resume(struct pci_dev *pci)
653 struct snd_card *card = pci_get_drvdata(pci);
654 struct oxygen *chip = card->private_data;
657 pci_set_power_state(pci, PCI_D0);
658 pci_restore_state(pci);
659 if (pci_enable_device(pci) < 0) {
660 snd_printk(KERN_ERR "cannot reenable device");
661 snd_card_disconnect(card);
666 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
667 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
668 for (i = 0; i < OXYGEN_IO_SIZE; ++i)
669 if (is_bit_set(registers_to_restore, i))
670 oxygen_write8(chip, i, chip->saved_registers._8[i]);
671 if (chip->has_ac97_0)
672 oxygen_restore_ac97(chip, 0);
673 if (chip->has_ac97_1)
674 oxygen_restore_ac97(chip, 1);
676 if (chip->model.resume)
677 chip->model.resume(chip);
679 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
681 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
684 EXPORT_SYMBOL(oxygen_pci_resume);
685 #endif /* CONFIG_PM */